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Dive into the research topics where Mamta Khosla is active.

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Featured researches published by Mamta Khosla.


Journal of Electronic Materials | 2016

Circuit Compatible Model for Electrostatic Doped Schottky Barrier CNTFET

Amandeep Singh; Mamta Khosla; Balwinder Raj

This paper proposes a circuit compatible model for electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET). The proposed model is an extension of the Schottky barrier carbon nanotube field effect transistor (SBCNTFET) to ED-SBCNTFET by adding polarity gates, which are used to create electrostatic doping. In ED-SBCNTFET, electrostatic doping is responsible for a fermi level shift of source and drain regions. A mathematical relation has been developed between fermi level shift and polarity gate bias. Both current–voltage (I–V) and capacitance–voltage (C–V) characteristics have been efficiently modeled. The results are compared with the reported semi-classical model and simulations from NanoTCAD ViDES for validation. The proposed model is much faster than numerical models as it denies self consistent equations. Finally, circuit application is demonstrated by simulating inverter using the proposed model in HSPICE.


ieee india conference | 2011

Analysis of leakage power reduction techniques in digital circuits

Anup Jalan; Mamta Khosla

With the advent of battery operated devices and scaling trends in deep submicron (DSM) regime, leakage power is becoming large component of total power dissipation. In this paper leakage reduction techniques viz. Stack forcing and Multi-Threshold CMOS (MTCMOS) have been implemented on CMOS, Complementary Pass Transistor Logic (CPL), and Transmission Gate (TG) logic style based digital circuits. The effects of these techniques are analysed and compared using NAND, MUX, XOR, and Full Adder circuits. MTCMOS approach showed significant leakage power reduction by the order of three in case of CMOS and modified TG logic style based circuits. MTCMOS approach was not effective in CPL style circuits as it was in CMOS and TG logic style circuits, in standby mode. In Stack forced approach, decent leakage power reduction is achieved with large delay overhead, for all CMOS, CPL and TG logic style based circuits. Designs and simulations were done on Cadence® Virtuoso® and Spectre® tools, using UMC 0.18 µm technology.


Microelectronics Journal | 2016

A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects

Sanjeev Kumar Sharma; Balwinder Raj; Mamta Khosla

This paper proposes an analytical subthreshold current model for undoped/lightly doped Cylindrical Nanowire FETs (CGNWFETS) including quantum effects. The model is derived from direct use of Gausss law, Drift Diffusion Approach (DDA) and effective Band Gap Widening (BGW). The Quantum Mechanical Effects (QMEs) are included in the model by taking the effects of BGW, which reduces the electron density in the subthreshold regime and reduces the subthreshold current consequently. The model explicitly shows how the oxide thickness, gate workfunction, and silicon thickness have an effect on the subthreshold current. The results obtained using proposed model is verified by comparison through SILVACO Atlas TCAD simulation; quite good agreement has been observed between model and numerical simulations results.


international conference on electronics computer technology | 2011

Analog realization of fuzzifier for IT2 fuzzy processor

Mamta Khosla; R. K. Sarin; Moin Uddin; Ajay K. Sharma

In this paper, design of CMOS based fuzzifier block for a general purpose Interval type-2 fuzzy processor is presented. The fuzzifier generates the Footprints of Uncertainty (FOU) for the input variables. It can implement four basic membership functions (MFs) viz. Z, trapezoidal, triangle and S. The characteristics (width, slope, position) of the lower and upper bounds of the FOU are easily adjustable. The simulations of the fuzzifier have been carried out by the Spectre tool of Cadence and the proposed design has been implemented for a two inputs function each having three MFs on 0.18um technology using Cadence Virtuoso Schematic/Layout Editor. Power consumption of the fuzzifier is 2.64mW and it occupies an area of 0.006mm.


Telecommunication Systems | 2018

Computational intelligence based localization of moving target nodes using single anchor node in wireless sensor networks

Parulpreet Singh; Arun Khosla; Anil Kumar; Mamta Khosla

Wireless Sensor Networks (WSNs) have tremendous ability to interact and collect data from the physical world. The main challenges for WSNs regarding performance are data computation, prolong lifetime, routing, task scheduling, security, deployment and localization. In recent years, many Computational Intelligence (CI) based solutions for above mentioned challenges have been proposed to accomplish the desired level of performance in WSNs. Application of CI provides independent and robust solutions to ascertain accurate node position (2D/3D) with minimum hardware requirement (position finding device, i.e., GPS enabled device). The localization of static target nodes can be determined more accurately. However, in the case of moving target nodes, accurate position of each node in network is a challenging problem. In this paper, a novel concept of projecting virtual anchor nodes for localizing the moving target node is proposed using applications of Particle Swarm Intelligence, H-Best Particle Swarm Optimization, Biogeography Based Optimization and Firefly Algorithm separately. The proposed algorithms are implemented for range-based, distributed, non-collaborative and isotropic WSNs. Only single anchor node is used as a reference node to localize the moving target node in the network. Once a moving target node comes under the range of a anchor node, six virtual anchor nodes with same range are projected in a circle around the anchor node and two virtual anchor nodes (minimum three anchor nodes are required for 2D position) in surrounding (anchor and respective moving target node) are selected to find the 2D position. The performance based results on experimental mobile sensor network data demonstrate the effectiveness of the proposed algorithms by comparing the performance in terms of the number of nodes localized, localization accuracy and scalability. In proposed algorithms, problem of Line of Sight is minimized due to projection of virtual anchor nodes.


Advances in Autism | 2017

Skin conductance response patterns of face processing in children with autism spectrum disorder

Anurag Sharma; Arun Khosla; Mamta Khosla; M Yogeshwara Rao

The purpose of this paper is to investigate the face processing responses of children with autism spectrum disorder (ASD) using skin conductance response (SCR) patterns and to compare it with typically developed (TD) children.,Two experiments have been designed to analyze the effect of face processing. In the first experiment, learned non-face (objects) vs unknown face stimuli have been shown and in the second experiment, familiar vs unfamiliar face stimuli have been shown to ten ASD and ten TD children and SCR patterns have been recorded, analyzed and compared for both the groups.,It has been observed that children with ASD were able to differentiate faces out of learned non-face stimuli and their SCR patterns were similar as TD children in the first experiment. In the second experiment, children with ASD were unable to recognize familiar faces from unfamiliar faces but TD children could easily discriminate between familiar and unfamiliar faces as their SCR patterns were different from children with ASD.,The present study advocates that impairment in face identification exists in children with ASD. Hence, it can be concluded that in children with ASD face processing is present but they do not recognize familiar faces or it can be said that face familiarization effect is absent in children with ASD.,There are very few findings that used SCR signal as main analysis parameter for face processing in children with ASD, in most of the studies; Electroencephalography signal has been used as analysis parameter. Moreover, familiar and unfamiliar face processing with multiple stimuli used in present work adds novelty to the literature.


Journal of Semiconductors | 2016

Compact model for ballistic single wall CNTFET under quantum capacitance limit

Amandeep Singh; Mamta Khosla; Balwinder Raj

This paper proposes a compact model for carbon nanotube field effect transistor (CNTFET) based on surface potential and conduction band minima. The proposed model relates the I – V characteristics to chirality under quantum capacitance limit. C – V characteristics have been efficiently modelled for different capacitance models which are used to find the relationship between CNT surface potential and gate voltage. The role of different capacitances is discussed and it has been found that the proposed circuit compact model strictly follows quantum capacitance limit. The proposed model is efficiently designed for circuit simulations as it denies self-consistent numerical simulation. Furthermore, this compact model is compared with experimental results. The model has been used to simulate an inverter using HSPICE.


Journal of Semiconductors | 2016

Modeling and simulation of carbon nanotube field effect transistor and its circuit application

Amandeep Singh; Dinesh Kumar Saini; Dinesh Agarwal; Sajal Aggarwal; Mamta Khosla; Balwinder Raj

The carbon nanotube field effect transistor (CNTFET) is modelled for circuit application. The model is based on the transport mechanism and it directly relates the transport mechanism with the chirality. Also, it does not consider self consistent equations and thus is used to develop the HSPICE compatible circuit model. For validation of the model, it is applied to the top gate CNTFET structure and the MATLAB simulation results are compared with the simulations of a similar structure created in NanoTCAD ViDES. For demonstrating the circuit compatibility of the model, two circuits viz. inverter and SRAM are designed and simulated in HSPICE. Finally, SRAM performance metrics are compared with those of device simulations from Nano TCAD ViDES.


International Journal of Swarm Intelligence | 2014

Evolutionary design of efficient type-2 fuzzy models from noisy data using hybrid PSO model

Mamta Khosla; R. K. Sarin; Moin Uddin

This work presents an efficient framework for designing type-2 fuzzy models from noisy data that represent majority of the real-world databases used for building models. The framework is based on the use of a hybrid particle swarm optimisation (PSO) model that combines the traits of gbest and lbest PSO variants for getting fast results and at the same time avoiding premature convergence. Two major components of the framework, i.e., the encoding mechanism, and the hybrid PSO model have been discussed. Further, two benchmark problems that cover major application domains of type-2 FLSs viz. forecasting and classification, have been presented to demonstrate the effectiveness of the proposed methodology. For each noisy benchmark data, type-1 fuzzy model is also designed and its performance is compared with the designed type-2 fuzzy model with an objective to exhibit better noise handling capability of type-2 models.


international conference on communication systems and network technologies | 2012

Identification of Type-2 Fuzzy Models for Time-Series Forecasting Using Particle Swarm Optimization

Mamta Khosla; R. K. Sarin; Moin Uddin

This paper presents the fuzzy model identification framework, where Particle Swarm Optimization (PSO) algorithm has been used as an optimization engine for building Type-2 fuzzy models from the available chaotic Mackeyâ-Glass time-series data. The presented framework is capable of evolving the Membership Functions parameters, Footprint of Uncertainty (FOU) and the rule set to obtain an optimized Type-2 fuzzy model. Four experiments are reported for differently corrupted chaotic time-series data sets. Root Mean square error (RMSE), between the outputs of the designed T2 FLS and the target is used as the performance criterion to rate the quality of solutions and hence demonstrate the performance of the proposed framework.

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Dive into the Mamta Khosla's collaboration.

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Balwinder Raj

Dr. B. R. Ambedkar National Institute of Technology Jalandhar

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R. K. Sarin

Dr. B. R. Ambedkar National Institute of Technology Jalandhar

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Arun Khosla

Dr. B. R. Ambedkar National Institute of Technology Jalandhar

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Moin Uddin

Delhi Technological University

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Anil Kumar

Chandigarh College of Engineering and Technology

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Parulpreet Singh

Dr. B. R. Ambedkar National Institute of Technology Jalandhar

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Harmandar Kaur

Guru Nanak Dev University

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Sanjeev Kumar Sharma

Dr. B. R. Ambedkar National Institute of Technology Jalandhar

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Ajay K. Sharma

National Institute of Technology Delhi

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Amit Gupta

Dr. B. R. Ambedkar National Institute of Technology Jalandhar

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