Balwinder Raj

Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect

In this paper the analysis of SNM, RNM, WNM and static power variation with width of access, load and driver have been carried out for nanoscale FinFET based SRAM cell. FinFET based SRAM design has been proposed as an alternative solution to the bulk devices. It can be inferred from the results that with increase in the width of driver FinFET, the high SNM reduces and low SNM increases. This is due the fact that the leakage current is considerably reduced due to increased control of the FinFET device structure, resulting relatively in highIon/Ioffratio. Further, the effect of process variation on the SRAM cell performance was analyzed using Monte Carlo simulation on HSPICE. The Monte Carlo simulation results for RNM and WNM to quantify the effect of process variation arising due to variation in FinFETs widths. The simulation was carried out for 1000 values, assuming 3σ equal to 10% of the mean value. Two structures of the FinFET viz. the standard PTM model and an underlapped FinFET have been also used for the simulations. It was identified that while the relative levels of the noise margins were lower for the underlapped case, the standard deviation was considerably lower too. In this work we also analyze the effect of temperature on noise margins and static power for FinFET based SRAM cell. FinFET is suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.

Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device

Purpose – The aim of this paper is to formulate the effect of the process variation on various leakage currents and subthreshold swing factor in FinFET devices. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies.Design/methodology/approach – Owing to large temperature variation within the die, the authors investigate the variation of various leakage currents with absolute die temperature.Findings – The results obtained on the basis of the model are compared and contrasted with reported numerical and experimental results. A close match was found which validates the analytical approach.Originality/value – The analytical modeling of subthreshold leakage current, subthreshold swing, gate leakage current and its variation with process parameters are carried out in this paper.

ONOFIC approach: low power high speed nanoscale VLSI circuits design

Shrinking in the device dimensions increases the device density on the chip and thus reducing the overall chip area requirement for logic implementation. Minimising the chip area is not a lonely optimisation performance factor for a VLSI chip designer. The other equally important performance parameters such that power dissipation and propagation delay are the thinkable facts for a designer. The focusable part of power dissipation is the huge leakage current in deep submicron (DSM) regime. Many leakage reduction techniques are applied to reduce the leakage current in the DSM regime but they have own limitations. Our proposed on/off logic (ONOFIC) approach gives an excellent settlement between power dissipation and propagation delay for designing the nanoscale CMOS circuits. It uses extra insertion of two transistors (an NMOS and a PMOS) within the logic block. The exact on/off level of the ONOFIC block improves the power dissipation and propagation delay of the logic circuits. In this article, ONOFIC approach is compared with the LECTOR leakage reduction technique and output results show that our proposed approach significantly reduces the power dissipation and enhancing the speed of the logic circuits with superior power-delay product.

Circuit Compatible Model for Electrostatic Doped Schottky Barrier CNTFET

This paper proposes a circuit compatible model for electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET). The proposed model is an extension of the Schottky barrier carbon nanotube field effect transistor (SBCNTFET) to ED-SBCNTFET by adding polarity gates, which are used to create electrostatic doping. In ED-SBCNTFET, electrostatic doping is responsible for a fermi level shift of source and drain regions. A mathematical relation has been developed between fermi level shift and polarity gate bias. Both current–voltage (I–V) and capacitance–voltage (C–V) characteristics have been efficiently modeled. The results are compared with the reported semi-classical model and simulations from NanoTCAD ViDES for validation. The proposed model is much faster than numerical models as it denies self consistent equations. Finally, circuit application is demonstrated by simulating inverter using the proposed model in HSPICE.

A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects

This paper proposes an analytical subthreshold current model for undoped/lightly doped Cylindrical Nanowire FETs (CGNWFETS) including quantum effects. The model is derived from direct use of Gausss law, Drift Diffusion Approach (DDA) and effective Band Gap Widening (BGW). The Quantum Mechanical Effects (QMEs) are included in the model by taking the effects of BGW, which reduces the electron density in the subthreshold regime and reduces the subthreshold current consequently. The model explicitly shows how the oxide thickness, gate workfunction, and silicon thickness have an effect on the subthreshold current. The results obtained using proposed model is verified by comparison through SILVACO Atlas TCAD simulation; quite good agreement has been observed between model and numerical simulations results.

Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach

Quantum mechanical analytical modeling for calculating the drain current of FinFET devices has been proposed in this paper. The work is presented for a FinFET structure with channel length of 30 nm, Fin height of 30 nm and Fin thickness of 20 nm. The variation of drain current with applied drain voltage and gate voltage for varying channel lengths and Fin thicknesses has also been evaluated. Our analytical modeling results were compared and contrasted with the reported experimental results in order to verify our proposed model. A close match was found which validates our analytical approach. The drain current has, also been, evaluated using the Synopsys TCAD tool Sentaurus and compared with the results obtained through our QM model.

Design and analysis of area efficient QCA based reversible logic gates

Abstract The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.

Single Electron Transistor theory: A review

In this paper theoretical concepts based on analytical models for Single Electron Transistor (SET) are presented. It has been observed that the fabrication technology has reached on its limits for the MOS feature size, beyond which further scaling of the channel is not achievable. Due to which SET is considered as the future of the complex IC fabrication by replacing MOS technology, having small quantum dot or island, instead of channel. Working of the SET is based on the Coulomb blockade principle which is the heart of the technology. Quantum mechanics is the physics used for explaining the tunnelling of single electron of SET, which says that the energy levels are quantized not continuous. Main reason behind the advancement in SET is the market requirement of the low power, high density and fast switching devices. These are possible by SET; no doubt speed is an issue for the memories designed with SET, with its low gain and high input impedance. In the review, mathematical model including tunnelling effect in junction, coulomb blockade, current equation, free energy equation based on Shcrodingers wave equation are presented.

Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction

FinFET are more versatile than traditional single-gate field effect transistors because it has two gates that can be controlled independently. Usually, the second gate of FinFET is used to dynamically control the threshold voltage of the first gate in order to improve circuit performance and reduce leakage power. A self-controllable-voltage-level (SVL) circuit which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in standby mode was developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. In this paper we propose new leakage power reduction techniques namely series LSVL (lower self controlled voltage level) and after using it, leakage power reduces 20 % for every increment of series transistor in lower ground connection. Leakage is found to contribute more amount of total power consumption in power-optimized FinFET logic circuits. This paper mainly deal with the various logic design styles to obtain the Leakage power savings through the judicious use of FinFET logic styles using NOR based design at 45 nm technology. FinFET circuits are superior in performance and produce less static power when compared to 32 nm circuits. FinFET can be designed at 32 nm. Finally, implementation of the schematics in CMOS NOR MODE, SG MODE, IG MODE, IG/LP MODE, LP MODE of NOR based FINFET is simulated by cadence virtuoso tools version 6.1 to obtain Leakage Power and Power Dissipation. By applying this we obtain 88 % Leakage power savings through the judicious use of FinFET logic styles having NOR based design at 45 nm technology.