Manabu Tsujimura

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 /spl mu/m by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than /spl plusmn/0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260/spl deg/C in N/sub 2/ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150/spl deg/C for 1000 h in N/sub 2/ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs.

Localized Oxidation of the Cu Surface after Chemical Mechanical Planarization Processing

After chemical mechanical planarization (CMP) processing of a Cu/low-k structure device, defects are often observed and some of them induce problems in manufacturing very large scale integrated circuit (VLSI) devices. As an example of defects, watermarks and protrusions on the Cu are detected. We found that the number of watermarks or protrusions is strongly affected by the cleaning conditions. The energy dispersive X-ray analysis (EDX) showed that these protrusions were composed of Cu and O. Moreover, atomic force microscopy (AFM) observations revealed that these protrusions grew during the storage time after the postcleaning. Electrochemical measurements also indicated that the protrusions were oxidized copper formed in the cleaning solutions due to the difference in corrosion current densities for various conditions of the Cu surface. Therefore, optimization of the post-CMP cleaning processing is a key issue for the reduction of defects such as protrusions.

Shear Stress Analyses in Chemical Mechanical Planarization with Cu/Porous Low-k Structure

In current LSI devices, porous low-k films are adopted as interlayer dielectrics (ILDs). However, the extremely low Youngs moduli of these films result in defects such as delamination, which are sometimes induced during chemical mechanical planarization (CMP). The main cause of delamination is thought to be shear stress induced by CMP downward pressure. In this study, we demonstrated that finite element method (FEM) results could be used to predict dangerous stress fields during CMP. It was revealed that shear stress concentrated on the ILD boundary with a large modulus difference. Moreover, stresses at dense lines were always lower than those at isolated lines. Furthermore, shear stress was sensitive to frictional force. The effect of a plasma-damaged layer on shear stress was quite limited. Consequently, these considerations provide a useful suggestion for future work on Cu/porous low-k-film fabrication as well as on the CMP of LSI devices.

Stress Analyses during Chemical Mechanical Planarization Processing with Cu/Porous Low-k Structures of LSI Devices

Porous low-k materials are required for the construction of 45-nm-node LSI devices. However, the extremely low Youngs modulus values of these materials result in the stress corrosion cracking (SCC) of the Cu interconnects during chemical mechanical planarization (CMP). We performed finite element method analyses of the stress at each step during the CMP. The results showed that the horizontal tensile stress was especially concentrated at the edges of the isolated fine wiring, and that higher tensile stresses appeared at the step of the barrier CMP. Moreover, the maximum values of the tensile stress increased with a decrease in Youngs modulus in the low-k films. The cause of the horizontal tensile stress was the downward CMP pressure, which indented the low-k films. These results suggest that CMP with a lower downward pressure and an LSI structure with a Cu dummy pattern were effective for avoiding SCC.

Electron beam inspection system for semiconductor wafer based on projection electron microscopy: II

Optical inspection systems and/or electron beam inspection systems are quite useful tools for the yield management in the semiconductor process. However, they have some issues of difficulties for the application to the yield management after 100nm-technology node generation. Optical inspection systems have a resolution limit by diffraction phenomena. On the other hand, electron beam inspection systems based on scanning electron microscopy (EBI-SEM) have the limit of inspection speed. Both limits are serious matter for the application to yield management after 100nm-technology node generation. We have developed the electron beam inspection system based on projection electron microscopy (EBI-PEM), having both performances of inspection speed of optical types and spatial resolution of EBI-SEM. The system has been improved on the signal electron collection efficiency and transmittance of the electron optical system. We also have developed high rate and sensitive signal detection system. Then we considered that the inspection speed of several times faster than the conventional EBI-SEM is feasible at the spatial resolution less than 100nm.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Electrochemical Reactions During Ru Chemical Mechanical Planarization and Safety Considerations

We analyzed electrochemical reactions during ruthenium (Ru) chemical mechanical planarization (CMP) using a potentiostat and a quartz crystal microbalance, and considered the potential safety issues. We evaluated the valence number derived from Faradays law using the dissolution mass change of Ru and total coulomb consumption in the electrochemical reactions for Ru in acidic solution and slurry. The valence numbers of dissolved Ru ions were distributed in the range of 2 to 3.5. As toxic ruthenium tetroxide (RuO4) has a valence number of 8, we were able to conclude that no toxic RuO4 was produced in the actual Ru CMP.

Stress Analysis of Dielectrics Using FEM for Analyzing the Cause of Cracking Observed After W-CMP

This study examined the cause of the mechanical fracture (cracking) of dielectrics observed after chemical mechanical polishing (CMP) in the damascene interconnect process for W/oxide structures through the stress analysis of dielectrics with the finite element method (FEM). The analysis, performed considering polishing pressure during CMP and residual film stress, revealed that the stress in dielectrics generated by polishing pressure during CMP was approximately 2% of that generated through W film removal. This result suggests a high likelihood that the cracking of dielectrics observed after CMP is caused by the release of residual stress in W film through CMP. To prevent the mechanical fracture of dielectrics, it is thus important to reduce defects in the deposition of dielectrics and to decrease residual film stress.

Analysis of CMP planarization performance for STI process

It has recently been reported that some waviness may affect STI CMP yield. CMP is designed primarily to planarize relatively with large r scale than small topography. However, there may be a range of wafer topographies in which STI patterns are over-polished, depending on peak-to-valley variations and frequencies. Permissible peak-to-valley variations and frequencies are calculated by determining whether the difference in polish quantities between the peak and valley is less than permissible values, such as 10 nm, 20 nm, and 30 nm. Reports indicate that slurry selectivity can decrease this effect, although with certain disadvantages.

Analysis on Copper Photocorrosion Induced by Illuminance in Chemical Mechanical Planarization Equipment Using Photodiode and Quartz Crystal Microbalance

Photoassisted corrosion of copper (Cu) was evaluated using a photodiode and a quartz crystal microbalance (QCM). A chip-type silicon (Si) photodiode with a large junction area was used in place of actual Si devices. When the illuminated photodiode was connected to the anode and cathode electrodes in an electrolyte, it worked as a voltage source between the two electrodes, and the corrosion rate was governed by the current between the electrodes. The corrosion rate is nearly proportional to the illuminance at less than 100 lx, and corrosion initiates at an illuminance as low as 1 lx. In the geometrical aspect of the photoassisted corrosion system, the corrosion rate is proportional to the square root of the area ratio of a P-connected Cu line to an N line, and is proportional to the illuminated area of the junction in a photodiode. The wavelength of the illuminating light markedly affects the photoassisted corrosion.