Manan Suri
Indian Institute of Technology Delhi
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Publication
Featured researches published by Manan Suri.
IEEE Transactions on Electron Devices | 2013
Manan Suri; Damien Querlioz; Olivier Bichler; Giorgio Palma; Elisa Vianello; Dominique Vuillaume; Christian Gamrat; Barbara DeSalvo
In this paper, we present an alternative approach to neuromorphic systems based on multilevel resistive memory synapses and deterministic learning rules. We demonstrate an original methodology to use conductive-bridge RAM (CBRAM) devices as, easy to program and low-power, binary synapses with stochastic learning rules. New circuit architecture, programming strategy, and probabilistic spike-timing dependent plasticity (STDP) learning rule for two different CBRAM configurations with-selector (1T-1R) and without-selector (1R) are proposed. We show two methods (intrinsic and extrinsic) for implementing probabilistic STDP rules. Fully unsupervised learning with binary synapses is illustrated through two example applications: 1) real-time auditory pattern extraction (inspired from a 64-channel silicon cochlea emulator); and 2) visual pattern extraction (inspired from the processing inside visual cortex). High accuracy (audio pattern sensitivity > 2, video detection rate > 95%) and low synaptic-power dissipation (audio 0.55 μW, video 74.2 μW) are shown. The robustness and impact of synaptic parameter variability on system performance are also analyzed.
international electron devices meeting | 2011
Manan Suri; Olivier Bichler; Damien Querlioz; O. Cueto; L. Perniola; Veronique Sousa; Dominique Vuillaume; Christian Gamrat; Barbara DeSalvo
We demonstrate a unique energy efficient methodology to use Phase Change Memory (PCM) as synapse in ultra-dense large scale neuromorphic systems. PCM devices with different chalcogenide materials were characterized to demonstrate synaptic behavior. Multi-physical simulations were used to interpret the results. We propose special circuit architecture (“the 2-PCM synapse”), read, write, and reset programming schemes suitable for the use of PCM in neural networks. A versatile behavioral model of PCM which can be used for simulating large scale neural systems is introduced. First demonstration of complex visual pattern extraction from real world data using PCM synapses in a 2-layer spiking neural network (SNN) is shown. System power analysis for different scaled PCM technologies is also provided.
international electron devices meeting | 2012
Manan Suri; Olivier Bichler; Damien Querlioz; Giorgio Palma; Elisa Vianello; Dominique Vuillaume; Christian Gamrat; Barbara DeSalvo
In this work, we demonstrate an original methodology to use Conductive-Bridge RAM (CBRAM) devices as binary synapses in low-power stochastic neuromorphic systems. A new circuit architecture, programming strategy and probabilistic STDP learning rule are proposed. We show, for the first time, how the intrinsic CBRAM device switching probability at ultra-low power can be exploited to implement probabilistic learning rule. Two complex applications are demonstrated: real-time auditory (from 64-channel human cochlea) and visual (from mammalian visual cortex) pattern extraction. A high accuracy (audio pattern sensitivity >2, video detection rate >95%) and ultra-low synaptic-power dissipation (audio 0.55μW, video 74.2μW) are obtained.
IEEE Transactions on Electron Devices | 2012
Olivier Bichler; Manan Suri; Damien Querlioz; Dominique Vuillaume; Barbara DeSalvo; Christian Gamrat
We introduce a novel energy-efficient methodology “2-PCM Synapse” to use phase-change memory (PCM) as synapses in large-scale neuromorphic systems. Our spiking neural network architecture exploits the gradual crystallization behavior of PCM devices for emulating both synaptic potentiation and synaptic depression. Unlike earlier attempts to implement a biological-like spike-timing-dependent plasticity learning rule with PCM, we use a simplified rule where long-term potentiation and long-term depression can both be produced with a single invariant crystallizing pulse. Our architecture is simulated on a special purpose event-based simulator, using a behavioral model for the PCM devices validated with electrical characterization. The system, comprising about 2 million synapses, directly learns from event-based dynamic vision sensors. When tested with real-life data, it is able to extract complex and overlapping temporally correlated features such as car trajectories on a freeway. Complete trajectories can be learned with a detection rate above 90 %. The synaptic programming power consumption of the system during learning is estimated and could be as low as 100 nW for scaled down PCM technology. Robustness to device variability is also evidenced.
Journal of Applied Physics | 2012
Manan Suri; Olivier Bichler; Damien Querlioz; B. Traoré; O. Cueto; L. Perniola; Veronique Sousa; Dominique Vuillaume; Christian Gamrat; Barbara DeSalvo
In this work, we demonstrate how phase change memory (PCM) devices can be used to emulate biologically inspired synaptic functions in particular, potentiation and depression, important for implementing neuromorphic hardware. PCM devices with different chalcogenide materials are fabricated and characterized. The asymmetry between the potentiation and depression behaviors of the PCM is stressed. Detailed multi-physical simulations are performed to study the underlying physics of the synaptic behavior of PCM. A versatile behavioral model and a multi-level circuit-compatible model are developed for system and circuit-level neuromorphic simulations. We propose a unique low-power methodology named the 2-PCM Synapse, to use PCM devices as synapses in large scale neuromorphic systems. To show the strength of our proposed solution, we efficiently simulated fully connected feed-forward spiking neural network capable of complex visual pattern extraction from real world data.
IEEE Transactions on Nanotechnology | 2015
Manan Suri; Vivek Parmar
In this paper, we show for the first time how unavoidable device variability of emerging nonvolatile resistive memory devices can be exploited to design efficient low-power, low-footprint extreme learning machine (ELM) architectures. In particular, we utilize the uncontrollable off-state resistance (Roff/HRS) spreads, of nanoscale filamentary-resistive memory devices, to realize random input weights and random hidden neuron biases; a characteristic requirement of ELM. We propose a novel RRAM-ELM architecture. To validate our approach, experimental data from different filamentary-resistive switching devices (CBRAM, OXRAM) are used for full-network simulations. Learning capability of our RRAM-ELM architecture is illustrated with the help of two real-world applications: 1) diabetes diagnosis test (classification) and 2) SinC curve fitting (regression).
international symposium on neural networks | 2011
Manan Suri; Veronique Sousa; L. Perniola; Dominique Vuillaume; Barbara DeSalvo
In this paper, we show that Phase Change Memory (PCM) can be used to emulate specific functions of a biological synapse similar to Long Term Potentiation (LTP) and Long Term Depression (LTD) plasticity effects. The dependence of synaptic weight on programming pulse width and pulse amplitude is shown experimentally for the PCM devices. Different combinations of consecutive LTD and LTP events have been experimentally demonstrated and analyzed for the PCM synapse.
international symposium on neural networks | 2015
Manan Suri; Vivek Parmar; Gilbert Sassine; Fabien Alibart
In this paper, we show how metal-oxide (OxRAM) based nanoscale memory devices can be exploited to design low-power Extreme Learning Machine (ELM) architectures. In particular we fabricated HfO2 and TiO2 based OxRAM devices, and exploited their intrinsic resistance spread characteristics to realize ELM hidden layer weights and neuron biases. To validate our proposed OxRAM-ELM architecture, full-scale learning and multi-class classification simulations were performed for two complex datasets: (i) Land Satellite images and (ii) Image segmentation. Dependence of classification performance on neuron gain parameter and OxRAM device properties was studied in detail.
international memory workshop | 2012
Manan Suri; Olivier Bichler; Q. Hubert; L. Perniola; V. Sousa; C. Jahan; D. Vuillaume; C. Gamrat; B. DeSalvo
In this work, we will focus on the use of Phase Change Memory (PCM) to emulate synaptic behavior in emerging neuromorphic system-architectures. In particular, we will originally show that the performance and energy-efficiency of large scale neuromorphic systems can be improved by engineering individual PCM devices used as synapses. This is obtained by adding a thin HfO2 interface layer to standard GST PCM devices, allowing for the lowering of the Set/Reset currents and the increase of the number of intermediate resistance states (or synaptic weights) in the synaptic potentiation characteristics. The experimentally obtained potentiation characteristics of such PCM devices are used to simulate a 2-layer ultra-dense spiking neural network (SNN) and to perform a complex visual pattern extraction from a test case based on real world data (i.e. cars passing on a 6-lane freeway). The total power dissipated in the learning mode, for the pattern extraction experiment is estimated to be as low as 60μW. Average detection rate of cars is found to be greater than 90%.
IEEE Transactions on Electron Devices | 2014
Giorgio Palma; Elisa Vianello; O. Thomas; Manan Suri; Santhosh Onkaraiah; A. Toffoli; C. Carabasse; M. Bernard; A. Roule; Onofrio Pirrotta; Gabriel Molas; Barbara De Salvo
In this paper, we show performance and reliability improvement of Ag- GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2-30-nm GeS2) leads to a resistance ratio (ROFF/RON) higher than 106 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications.