Vivek Parmar

Exploiting Intrinsic Variability of Filamentary Resistive Memory for Extreme Learning Machine Architectures

In this paper, we show for the first time how unavoidable device variability of emerging nonvolatile resistive memory devices can be exploited to design efficient low-power, low-footprint extreme learning machine (ELM) architectures. In particular, we utilize the uncontrollable off-state resistance (Roff/HRS) spreads, of nanoscale filamentary-resistive memory devices, to realize random input weights and random hidden neuron biases; a characteristic requirement of ELM. We propose a novel RRAM-ELM architecture. To validate our approach, experimental data from different filamentary-resistive switching devices (CBRAM, OXRAM) are used for full-network simulations. Learning capability of our RRAM-ELM architecture is illustrated with the help of two real-world applications: 1) diabetes diagnosis test (classification) and 2) SinC curve fitting (regression).

OXRAM based ELM architecture for multi-class classification applications

In this paper, we show how metal-oxide (OxRAM) based nanoscale memory devices can be exploited to design low-power Extreme Learning Machine (ELM) architectures. In particular we fabricated HfO2 and TiO2 based OxRAM devices, and exploited their intrinsic resistance spread characteristics to realize ELM hidden layer weights and neuron biases. To validate our proposed OxRAM-ELM architecture, full-scale learning and multi-class classification simulations were performed for two complex datasets: (i) Land Satellite images and (ii) Image segmentation. Dependence of classification performance on neuron gain parameter and OxRAM device properties was studied in detail.

Neuromorphic hybrid RRAM-CMOS RBM architecture

Restricted Boltzmann Machines (RBMs) offer a key methodology to implement Deep Learning paradigms. This paper presents a novel approach for realizing a hybrid RRAM-CMOS RBM architecture. In our proposed hybrid RBM architecture, HfOx based (filamentary-type switching) RRAM devices are extensively used to implement: (i) Synapses (ii) Internal neuron-state storage and (iii) Stochastic neuron activation function. To validate the proposed scheme we simulated our RBM architecture for classification and reconstruction of hand-written digits on a reduced MNIST dataset of 6000 images. Contrastive-divergence (CD) specially optimized for RRAM devices was used to drive the synaptic weight update mechanism. Total required size of the RRAM matrix in the simulated application is of the order of ~ 0.4 Mb. Peak classification accuracy of 92 %, and an average accuracy of ~ 89 % was obtained over 100 training epochs. Average number of RRAM switching events was ~ 14 million/per epoch.

Hybrid CMOS-OxRAM RNG circuits

Compact, low-power random number generators (RNG) are essential for applications such as stochastic, bio-inspired-computing and secure system data encryption/communication. We demonstrate for the first time highly scalable RNG circuits based on the reset-state transient current fluctuation of resistive switching OxRAM devices. We propose- (i) single OxRAM based pseudo-random number generator (PRNG) and (ii) 2-OxRAM based true-random number generator (TRNG) circuits. The proposed hybrid RNG circuits have been validated for 10 nm thick HfOx devices at 180 nm CMOS node. Chi-square test, serial spectral test and covariance/correlation-based analysis are performed to analyze the performance of the proposed hybrid RNG nanocircuits.

Neuromorphic Hardware Accelerated Adaptive Authentication System

In this paper we present a multimodal authentication (person identification) system based on simultaneous recognition of face and speech data using a novel bio-inspired architecture powered by the CM1K chip. The CM1K chip has a constant recognition time irrespective of the size of the knowledge base, which gives massive time gains in learning and recognition over software implementations of similar methods. We demonstrate a system utilizing the CM1K chip as a neural network accelerator along with data pre-processing done by a desktop PC. The system realized consumes energy of the order: 668 μJ for learning and 487 μJ for recognition, while operating at 25 MHz. The classification test accuracy of the system is approximately 91%.

Design Exploration of IoT centric Neural Inference Accelerators

Neural networks have been successfully deployed in a variety of fields like computer vision, natural language processing, pattern recognition, etc. However most of their current deployments are suitable for cloud-based high-performance computing systems. As the computation of neural networks is not suited to traditional Von-Neumann CPU architectures, many novel hardware accelerator designs have been proposed in literature. In this paper we present the design of a novel, simplified and extensible neural inference engine for IoT systems. We present a detailed analysis on the impact of various design choices like technology node, computation block size, etc on overall performance of the neural inference engine. The paper demonstrates the first design instance of a power-optimized ELM neural network using ReLU activation. Comparison between learning performance of simulated hardware against the software model of the neural network shows a variation of ~ 1% in testing accuracy due to quantization. The accelerator compute blocks manage to achieve a performance per Watt of ~ 290 MSPS/W (Million samples per second per Watt) with a network structure of size: 8 x 32 x 2. Minimum energy of 40 pJ is acheived per sample processed for a block size of 16. Further, we show through simulations that an added power-saving of ~ 30 % can be acheived if SRAM based main memory is replaced with emerging STT-MRAM technology.

Exploiting Variability in Resistive Memory Devices for Cognitive Systems

In literature, different approaches point to the use of different resistive memory (RRAM) device families such as PCM [1], OxRAM, CBRAM [2], and STT-MRAM [3] for synaptic emulation in dedicated neuromorphic hardware. Most of these works justify the use of RRAM devices in hybrid learning hardware on grounds of their inherent advantages, such as ultra-high density, high endurance, high retention, CMOS compatibility, possibility of 3D integration, and low power consumption [4]. However, with the advent of more complex learning and weight update algorithms (beyond-STDP kinds), for example the ones inspired from Machine Learning, the peripheral synaptic circuit overhead considerably increases. Thus, use of RRAM cannot be justified on the merits of device properties alone. A more application-oriented approach is needed to further strengthen the case of RRAM devices in such systems that exploit the device properties also for peripheral nonsynaptic and learning circuitry, beyond the usual synaptic application alone.In this chapter, we discuss two novel designs utilizing the inherent variability in resistive memory devices to successfully implement modified versions of Extreme Learning Machines and Restricted Boltzmann Machines in hardware.

An energy-efficient hybrid (CMOS-MTJ) TCAM using stochastic writes for approximate computing

We propose a novel writing scheme for hybrid CMOSMTJ TCAM cells to achieve low write energy for approximate computing applications, by exploiting the noise tolerant behavior of such computational paradigms. We show that by exploiting stochastic MTJ switching TCAM cell write energy and latency can be improved. In particular, for an n-bit TCAM, used for approximate computing application, the least significant bits (LSBs) can be operated with weak stochastic write conditions without a significant drop on match accuracy. Distance match accuracy for a 3-bit (LSB), 4T-2MTJ TCAM, designed using 90 nm CMOS technology node and 57 nm (diameter) perpendicular magnetic anisotropic (PMA) MTJ devices was investigated. Using a write probability of 0.97, the overall write energy per LSB was decreased by a factor of 2.3 x, while keeping the cell write latency 7 ns. Impact of MTJ device variability on TCAM cell parameters such as search noise margin (NM) was also analyzed.