Mandana Tadayoni

A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability

In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.

SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells

Embedded Flash NVM has become a key component in many applications, such as data processing, industrial electronics, automotive electronics, consumer electronics and wireless communications. SuperFlash® technology is based on the split-gate concept, using source-side electron injection for programming. The aim of this work is to propose, for the first time, a SPICE macro-model of the 2T (Select Gate and Floating Gate) 3rd generation SuperFlash cell [Hidaka], implemented in a 55 nm CMOS technology. A parameter extraction procedure is also proposed, showing a good agreement between the model and measurements.

Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor

In this paper we discuss key challenges related to application of an accurate 2T cell model for robust array design in 40nm CMOS technology and how an improved model behavior is used to overcome the challenges. The main challenge is the extraction of model parameters for word line (WL) and floating gate (FG) transistors in the absence of access to the FG. A global optimization scheme with an improved data collection strategy enabled the extraction of a comprehensive set of model parameters. This makes the separation of mobility parameters of WL and FG transistors possible.

A novel test structure to implement a programmable logic array using split-gate flash memory cells

We developed a novel configurable logic array test structure using a highly scalable 3rd generation split-gate flash memory cell that features low power and fast configuration time. This split-gate SuperFlash® configuration element (SCE) has been demonstrated with a 90nm embedded Flash technology. The resulting SCE eliminates the need for esoteric fabrication process, and sensing, and SRAM circuits and reduces configuration time for programmable arrays (PA) such as FPGAs and CPLDs. Additionally, SCE inherently ports the advantages of SSTs split-gate Flash memory technology with compact area, low-voltage read operation, low-power poly-to-poly erase and source-side channel hot electron (SSCHE) injection programming mechanisms, along with superior reliability.