Chien-Sheng Su
Microchip Technology
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Chien-Sheng Su.
international memory workshop | 2015
Nhan Do; Latt Tee; Santosh Hariharan; Steven Lemke; Mandana Tadayoni; Will Yang; Man-Tang Wu; Jinho Kim; Yueh-Hsin Chen; Chien-Sheng Su; Vipin Tiwari; Stephen Zhou; Rodger Qian; Ian Yue
In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.
Archive | 2013
Xian Liu; Mandana Tadayoni; Chien-Sheng Su; Nhan Do
Archive | 2016
Jeng-Wei Yang; Chun-Ming Chen; Man-Tang Wu; Feng Zhou; Xian Liu; Chien-Sheng Su; Nhan Do
Archive | 2014
Chien-Sheng Su; Hieu Van Tran; Mandana Tadayoni; Nhan Do
Archive | 2012
Willem-Jan Toren; Xian Liu; Gerhard Metzger-Brueckl; Nhan Do; Stephan Wege; Nadia Miridi; Chien-Sheng Su; Cecile Bernardi; Liz Cuevas; Florence Guyot; Yueh-Hsin Chen; Henry Om'mani; Mandana Tadayoni
Archive | 2017
Jeng-Wei Yang; Man-Tang Wu; Chun-Ming Chen; Mandana Tadayoni; Chien-Sheng Su; Nhan Do
Archive | 2016
Man-Tang Wu; Jeng-Wei Yang; Chien-Sheng Su; Chun-Ming Chen; Nhan Do
Archive | 2017
Jinho Kim; Chien-Sheng Su; Feng Zhou; Xian Liu; Nhan Do; Prateep Tuntasood; Parviz Ghazavi
Archive | 2017
Chien-Sheng Su; Jeng-Wei Yang; Feng Zhou
Archive | 2017
Feng Zhou; Xian Liu; Jeng-Wei Yang; Chien-Sheng Su; Nhan Do
