Is this you? Create Your Porfile
Avatar

Chien-Sheng Su

Microchip Technology

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Explore More

Hotspot

Dive into the research topics where Chien-Sheng Su is active.

Explore More

Publication

Featured researches published by Chien-Sheng Su.

international memory workshop | 2015

A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability

Nhan Do; Latt Tee; Santosh Hariharan; Steven Lemke; Mandana Tadayoni; Will Yang; Man-Tang Wu; Jinho Kim; Yueh-Hsin Chen; Chien-Sheng Su; Vipin Tiwari; Stephen Zhou; Rodger Qian; Ian Yue

In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.

Archive | 2013

Method of forming a memory cell by reducing diffusion of dopants under a gate

Xian Liu; Mandana Tadayoni; Chien-Sheng Su; Nhan Do

Archive | 2016

Method Of Forming Self-Aligned Split-Gate Memory Cell Array With Metal Gates And Logic Devices

Jeng-Wei Yang; Chun-Ming Chen; Man-Tang Wu; Feng Zhou; Xian Liu; Chien-Sheng Su; Nhan Do

Archive | 2014

Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same

Chien-Sheng Su; Hieu Van Tran; Mandana Tadayoni; Nhan Do

Archive | 2012

Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory Array And A Method Of Forming Such Structure

Willem-Jan Toren; Xian Liu; Gerhard Metzger-Brueckl; Nhan Do; Stephan Wege; Nadia Miridi; Chien-Sheng Su; Cecile Bernardi; Liz Cuevas; Florence Guyot; Yueh-Hsin Chen; Henry Om'mani; Mandana Tadayoni

Archive | 2017

Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing

Jeng-Wei Yang; Man-Tang Wu; Chun-Ming Chen; Mandana Tadayoni; Chien-Sheng Su; Nhan Do

Archive | 2016

Method Of Forming Split-Gate Memory Cell Array Along With Low And High Voltage Logic Devices

Man-Tang Wu; Jeng-Wei Yang; Chien-Sheng Su; Chun-Ming Chen; Nhan Do

Archive | 2017

METHOD OF FORMING MEMORY ARRAY AND LOGIC DEVICES

Jinho Kim; Chien-Sheng Su; Feng Zhou; Xian Liu; Nhan Do; Prateep Tuntasood; Parviz Ghazavi

Archive | 2017

Non-volatile Split Gate Memory Cells With Integrated High K Metal Gate Logic Device And Metal-Free Erase Gate, And Method Of Making Same

Chien-Sheng Su; Jeng-Wei Yang; Feng Zhou

Archive | 2017

Non-volatile split gate memory cells with integrated high K metal gate, and method of making same

Feng Zhou; Xian Liu; Jeng-Wei Yang; Chien-Sheng Su; Nhan Do

Explore More

Collaboration

Dive into the Chien-Sheng Su's collaboration.

Top Co-Authors
Avatar

Nhan Do

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Mandana Tadayoni

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Jeng-Wei Yang

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Man-Tang Wu

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Xian Liu

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Chun-Ming Chen

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Yueh-Hsin Chen

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Feng Zhou

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Hieu Van Tran

Microchip Technology

View shared research outputs
Top Co-Authors
Avatar

Cecile Bernardi

Microchip Technology

View shared research outputs
Explore More
Researchain Logo
Decentralizing Knowledge