Nhan Do

Redesigning commercial floating-gate memory for analog computing applications

We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 μm2. While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in state-of-the-art analog circuit implementations. The new memory cell arrays have been successfully tested, in particular confirming that each cell may be automatically tuned, with ~1% precision, to any desired subthreshold readout current value within an almost three-orders-of-magnitude dynamic range, even using an unoptimized tuning algorithm. Preliminary results for a four-quadrant vector-by-matrix multiplier, implemented with the modified memory array, gate-coupled with additional peripheral floating-gate transistors, show highly linear transfer characteristics over a broad range of input currents.

A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability

In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.

Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells

We have fabricated and successfully tested an analog vector-by-matrix multiplier, based on redesigned 10×12 arrays of 55 nm commercial NOR flash memory cells. The modified arrays enable high-precision individual analog tuning of each cell, with sub-1% accuracy, while keeping the highly optimized cells, with their long-term state retention, intact. The array has an area of 0.33 μm2 per cell, and is at least one order of magnitude more dense than the reported prior implementations of nonvolatile analog memories. The demonstrated vector-by-vector multiplier, using gate coupling to additional periphery cells, has ∼2% precision, limited by the aggregate effect of cell noise, retention, mismatch, process variations, tuning precision, and capacitive crosstalk. A differential version of the multiplier has allowed us to demonstrate sub-3% temperature drift of the output signal in the range between 25 °C and 85 °C.

Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers

This paper for the first time successfully demonstrates a Logic-compatible, highly reliable, automotive-grade 16Mb flash macro with self- aligned, split-gate FG-based flash cell embedded into a 40nm Low Power CMOS with copper low-K interconnects. Key Features of the flash macro: Dual power supply with operation temperature from -40 to 150oC; Random Read access 10ns @ worst case condition; Low active and standby power; High raw endurance and data retention lifetime before using ECC. This technology provides large read current window which is compatible with both automotive MCU markets and low power mode tailored for smart card/industrial applications. The 16Mb Design test chip (DTC) with industry-leading cell size has demonstrated functionality with tight cell Vt and read current distributions. The SG NVM cell and erase gate are processed with self-alignment to gate spacer and polysilicon CMP (Chemical Mechanical Polishing) that can be easily integrated in a modular way to the standard logic process.

Common-floating gate test structure for separation of cycling-induced degradation components in split-gate flash memory cells

The program-erase cycling-induced degradation mechanisms in a split-gate SuperFlash® memory cell were analyzed using a test structure containing two cells with a common floating gate. This test structure allowed us to separate the degradation mechanisms taking place in the floating-gate oxide and tunnel oxide during cycling. It was demonstrated that the program-induced floating gate oxide degradation becomes less significant for the advanced SuperFlash technology, which uses lower programming voltage.

Model-based high-precision tuning of NOR flash memory cells for analog computing applications

High-precision individual cell tuning was experimentally demonstrated, for the first time, in analog integrated circuits redesigned from a commercial NOR flash memory. The tuning is fully automatic, and relies on a write-verify algorithm, with the optimal amplitude of each write pulse determined from runtime measurements, using a compact model of cells dynamics, fitted to experimental results. The algorithm has allowed tuning of each cell of a 100-cell array to any desired state within a 4-orders-of-magnitude dynamic range. With 10 write pulses, the average tuning accuracy is about 3%, while with 35 pulses the precision reaches ~0.3%. Taking into account the dynamic range, the last number is equivalent to ~1,500 levels, i.e. 10+ bits.

SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells

Embedded Flash NVM has become a key component in many applications, such as data processing, industrial electronics, automotive electronics, consumer electronics and wireless communications. SuperFlash® technology is based on the split-gate concept, using source-side electron injection for programming. The aim of this work is to propose, for the first time, a SPICE macro-model of the 2T (Select Gate and Floating Gate) 3rd generation SuperFlash cell [Hidaka], implemented in a 55 nm CMOS technology. A parameter extraction procedure is also proposed, showing a good agreement between the model and measurements.

eNVM Technologies Scaling Outlook and Emerging NVM Technologies for Embedded Applications

In this paper, scaling prospects and challenges of existing embedded non-volatile memory (eNVM) technologies are discussed. The impact of both lateral and vertical memory cell scaling on performance and reliability will be described for various types of nitride based and floating gate embedded NVM cells. Different types of emerging NVM technologies will also be discussed as potential options to replace traditional NVM technologies in embedded applications for sub-20nm process nodes and beyond.

Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor

In this paper we discuss key challenges related to application of an accurate 2T cell model for robust array design in 40nm CMOS technology and how an improved model behavior is used to overcome the challenges. The main challenge is the extraction of model parameters for word line (WL) and floating gate (FG) transistors in the absence of access to the FG. A global optimization scheme with an improved data collection strategy enabled the extraction of a comprehensive set of model parameters. This makes the separation of mobility parameters of WL and FG transistors possible.

Split-Gate Floating Poly SuperFlash ® Memory Technology, Design, and Reliability

Split-gate embedded flash memory technology has been around for a couple of decades and has become a de facto standard for embedded products such as microcontrollers and smart cards. The majority of the large microcontroller and smartcard chip-makers and a series of fabless companies are now using some form of a split-gate embedded flash-memory technology because of its advantages in power, performance, and cost compared with traditional EEPROM or stacked-gate solutions. This chapter covers the fundamentals of split-gate embedded flash memories with an emphasis on SST’s widely adopted SuperFlash® memory technology as an example to demonstrate the benefits of a split-gate embedded flash-memory technologies. The fundamentals of SuperFlash technology, design, reliability, and scalability are discussed in detail in various sections, which would provide a detailed understanding of a split-gate, embedded flash-memory technology.