Manjit Borah

An edge-based heuristic for Steiner routing

A new approximation heuristic for finding a rectilinear Steiner tree of a set of nodes is presented. It starts with a rectilinear minimum spanning tree of the nodes and repeatedly connects a node to the nearest point on the rectangular layout of an edge, removing the longest edge of the loop thus formed. A simple implementation of the heuristic using conventional data structures is compared with previously existing algorithms. The performance (i.e., quality of the route produced) of our algorithm is as good as the best reported algorithm, while the running time is an order of magnitude better than that of this best algorithm. It is also shown that the asymptotic time complexity for the algorithm can be improved to O(n log n), where n is the number of points in the set. >

Transistor sizing for low power CMOS circuits

A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the power dissipation of a circuit in terms of the transistor size is derived which includes both the capacitive and the short circuit power dissipation. SPICE circuit simulation results are presented to confirm the correctness of the analytical model. Based on the intuitions drawn from the analytical model, heuristics for initial transistor sizing on critical and noncritical paths for minimum power consumption are developed. Further, fast heuristics to perform transistor sizing in CMOS circuits for minimizing power consumption while meeting the given delay constraints are presented.

Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fan-out load should be enlarged to minimize the power consumption of the circuit. We derive analytical formulation for computing the power optimal size of a transistor and isolate the factor a ecting the power optimal size. We extend our model to analyze powerdelay characteristic of a CMOS circuit and derive the power-delay optimal size of a transistor. Based on our model we develop heuristics to perform transistor sizing in CMOS layouts for minimizing power consumption while meeting given delay constraints. Experimental results (SPICE simulations) are presented to con rm the correctness of our analytical model.

A SIMD solution to the sequence comparison problem on the MGAP

Molecular biologists frequently compare an unknown biosequence with a set of other known biosequences to find the sequence which is maximally similar, with the hope that what is true of one sequence, either physically or functionally, could be true of its analogue. Even though efficient dynamic programming algorithms exist for the problem, when the size of the database is large, the time required is quite long, even for moderate length sequences. In this paper, we present an efficient pipelined SIMD solution to the sequence alignment problem on the Micro-Grain Array Processor (MGAP), a fine-grained massively parallel array of processors with nearest-neighbor connections. The algorithm compares K sequences of length O(M) with the actual sequence of length N, in O(M+N+K) time with O(MN) processors, which is AT-optimal. The implementation on the MGAP computes at the rate of about 0.1 million comparisons per second for sequences of length 128.<<ETX>>

Accurate Estimation of Combinational Circuit Activity

Several techniques to estimate power consumption of a combinational circuit using probabilistic methods have been proposed. However none of these techniques take into account circuit activity when two or more inputs change simultaneously or when glitching occurs. A formulation is presented in this paper which includes signal correlation and multiple gate input switching. Work is also presented in estimating the glitching contribution to the switching activity. Results obtained from benchmarks and test circuits show very good accuracy when compared to actual activities as measured by SPICE and IRSIM.

High-throughput and low-power DSP using clocked-CMOS circuitry

We argue that the clocked-CMOS (CMOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market of portable electronics. By the virtue of self latching gates allowing very ne-grained pipelining, avoidance of precharge and short circuit power consumption, the CMOS circuit o ers very good powerdelay e ciency. We support our claims through the design of an 8-bit unsigned binary multiplier with pipelining at the gate level which can produce 500 million multiplications per second consuming only 0.8 W power using 1.0 micron technology and 3.3V power supply. By comparison the fastest previously existing pipelined multiplier has a throughput rate of 400 million multiplications per second consuming 0.8 W power at 0.8 micron technology, 5V, using wave-pipelining.

Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering

In this paper we present new techniques to reduce the power consumption of a static CMOS circuit by enlarging transistors in high fan-out gates and reordering inputs to the gates. The techniques are developed based on observations from results of hspice simulations. These methods are incorporated into a performance and power constrained module generator, PowerSizer. Experimental results from the module generator on several real circuits show that as much as 15% saving in power consumption can be obtained on arithmetic circuits with almost no tradeoff in area or delay.

Two-Stage Newton–Raphson Method for Transistor-Level Simulation

In this paper, we introduce an efficient transistor-level simulation tool with SPICE-accuracy for deep-submicrometer very large-scale integration circuits with strong-coupling effects. The new approach uses multigrid for huge networks of power/ground, clock, and interconnect with strong coupling. Mutual inductance can be incorporated without error-prone matrix sparsification approximations or expensive matrix inversion. Transistor devices are integrated using a novel two-stage Newton-Raphson method to dynamically model the linear network and nonlinear devices boundary. Orders-of-magnitude speedup over Berkeley SPICE3 is observed for sets of real deep-submicrometer design circuits

Edge detection using fine-grained parallelism in VLSI

The authors demonstrate an optimal time algorithm and architecture for edge detection in real time using fine grained parallelism. Given an image in the form of a two-dimensional array of pixels, this algorithm computes the Sobel and Laplacian operators for skimming lines in the image and then generates the Hough array using thresholding Hough transforms for M different angles of projection are obtained in a fully systolic manner without using any multiplication or division. An implementation of the algorithm on the MGAP-a fine-grained processor array architecture developed at the Pennsylvanian State University-is shown. It computes at the rate of approximately 75000 Hough transforms per second on a 256*256 image using a 25-MHz clock. It is also shown that the algorithm can be easily extended to the general case of Radon transforms.<<ETX>>

Fast algorithm for performance-oriented Steiner routing

We present a routing algorithm which minimizes the Elmore delay to the identified critical sinks while producing routes comparable to the best previously existing Steiner router. Since performance oriented layout generators employ iterative techniques that require a large number of calls to the routing algorithm for layout evaluation, a fast algorithm for routing is desirable. Our algorithm has a fast (O(n/sup 2/), where n is the number of points) and practical implementation using simple data structures and techniques. Comparisons with other existing algorithms are presented along with results from a performance driven layout generator using our routing algorithm.