Raminder Singh Bajwa

Architecture-level power estimation and design experiments

Architecture-level power estimation has received more attention recently because of its efficiency. This article presents a technique used to do power analysis of processors at the architecture level. It provides cycle-by-cycle power consumption data of the architecture on the basis of the instruction/data flow stream. To characterize the power dissipation of control units, a novel hierarchical method has been developed. Using this technique, a power estimator is implemented for a commercial processor. The accuracy of the estimator is validated by comparing the power values it produces against measurements made by a gate-level power simulator for the same benchmark set. Our estimation approach is shown to provide very efficient and accurate power analysis at the architecture level. The energy models built for first-pass estimation (such as ALU, MAC unit, register files) are reusable for future architecture design modification. In this article, we demonstrate the application of the technique. Furthermore, this technique can evaluate various kinds of software to achieve hardware/software codesign for low power.

A SIMD solution to the sequence comparison problem on the MGAP

Molecular biologists frequently compare an unknown biosequence with a set of other known biosequences to find the sequence which is maximally similar, with the hope that what is true of one sequence, either physically or functionally, could be true of its analogue. Even though efficient dynamic programming algorithms exist for the problem, when the size of the database is large, the time required is quite long, even for moderate length sequences. In this paper, we present an efficient pipelined SIMD solution to the sequence alignment problem on the Micro-Grain Array Processor (MGAP), a fine-grained massively parallel array of processors with nearest-neighbor connections. The algorithm compares K sequences of length O(M) with the actual sequence of length N, in O(M+N+K) time with O(MN) processors, which is AT-optimal. The implementation on the MGAP computes at the rate of about 0.1 million comparisons per second for sequences of length 128.<<ETX>>

Validation of an architectural level power analysis technique

This paper presents a technique used to do po wer analysis of a real p rocessor at the architectural lev el. The target processor in tegrates a 16-bit DSP an d a 32-bit RISC on a single c hip. O ur po wer estimator pro vides po wer consumption data of the architecture based on the instruction/data flo w stream We demonstrat e the accuracy of the estimator by com paring the po wer valu es it p roduces against measurem en tsm adeby a gate level po wer sim ulator for th e same benc hmark set. Our estimation approac h has been shown to pro vide v ery efficient accurate pow er an alysis at the architectural level.

A unified approach in the analysis of latches and flip-flops for low-power systems

In this paper we propose a set of rules for consistent estimation of the real performance and power features of the latch and flip-flop structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for low-power and high-performance applications.

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

This paper presents a new pipeline structure that dramatically reduces the power consumption of multimedia processors by using the commonly observed characteristic that most of the execution cycles of signal processing programs are used for loop executions. In our pipeline, the signals obtained by decoding the instructions included in a loop are temporarily stored in a small-capacity RAM that we call decoded instruction buffer (DIB), and are reused at every cycle of the loop iterations. The power saving is achieved by stopping the instruction fetch and decode stages of the processor during the loop execution except its first iteration. The result of our power analysis shows that about 40% power saving can be achieved when our pipeline structure is incorporated into a digital signal processor or RISC processor. The area of the DIB is estimated to be about 0.7 mm/sup 2/ assuming triple-metal 0.5 /spl mu/m CMOS technology.

Image processing with the MGAP: a cost effective solution

Image processing applications are suitable candidates for parallelism and have at least in part motivated the design and development of some of the pioneering massively parallel processing systems including the CLIP family, the DAP, the MPP and the GAPP. By exploiting design techniques and architectures suitable for VLSI technology one can now build hardware which provides comparable performance at a fraction of the cost it took for these earlier designs. The authors describe the use of a fine-grained, massively parallel VLSI processor array, the Micro-Grained Array Processor (MGAP) for image processing applications. The array and its support systems, in their current configuration, are designed to be used as a co-processor board in a desk-top workstation. The array can be used for applications other than image processing as well. The versatility of the array and the single broad design provide a cost effective solution for a variety of parallelizable tasks.<<ETX>>

Comparative analysis of latches and flip-flops for high-performance systems

In this paper we propose a set of rules for consistent estimation of the real performance and power features of the latch and flip-flop structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance applications.

Computer vision on the MGAP

The authors show that the MGAP can be used to solve a variety of problems in computer vision. It provides performance similar to the MPP, the CLIP, the DAP and the GAPP at a fraction of their cost. At the same time, the MGAP is general purpose enough to be used in a variety of other fields also. As might be expected, the MGAP is very well suited for low-level vision tasks, but is not ideal for tasks requiring global information, such as histogramming. A shift-register network is proposed as an addition to the array architecture to improve global communications. This results in a factor of 20 performance improvement for histogram computation. The MGAP prototype is currently being tested. The custom micro-grain PGAs and the board have been fabricated. The authors have a simulator for the processor array which operates at the level of the assembly code. They have developed both high and low level programming tools. A new language called /sup */C++ is used to program the MGAP. It extends C++ to handle parallel data and specify data movement in a concise and natural manner. The compiler generates code for the processor array, the controller as well as the scalar processor.

Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

While power consumption has become an important design constraint very few reports of power analysis of processors are available in the literature. The processor considered is an experimental integration of a 16-bit DSP and a 32-bit RISC microcontroller, ERDI. Simulation based power analysis on a back annotated design is used to obtain data for a set of DSP application kernels and synthetic benchmarks.

Architectural level hierarchical power estimation of control units

This paper presents a novel technique used to estimate the power dissipation of control units at the architectural level. Based on the instruction stream and output signals of the control units, this approach provides accurate power consumption data without any knowledge of their logic structures. It is a top-down hierarchical method which can handle random logic control units as well as ROM and PLA based control units. The upper-level power estimation analyses the instructions through their formats, and produces an efficient energy model for instruction format transitions. The lower-level estimation is performed for each instruction format by tracing the transitions of output signals. For simple logic control units, predictable internal signals can be used instead of output signals. We have applied this technique into an architectural level power estimator of a real processor. The accuracy of the estimator is demonstrated by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. The results show that our estimation approach for control units can provide more accurate solution than statistical analysis and is more efficient than conventional look-up table based methods.