Ernest S. Kuh

Efficient Algorithms for Channel Routing

In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.

Clock routing for high-performance ICs

In this paper we focus on routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of gate, etc.…) ASICs. In previously reported work, the routing of the clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock routing problems. We present a novel approach to clock routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions we have proven theoretically and observed experimentally a decrease in skew with an increase in net size. In practice, we have observed a two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree.

The state-variable approach to network analysis

The universality of the state-variable approach to network analysis is demonstrated in general discussions and specific examples. The method of formulation of the state equations for an arbitrary lumped, linear, finite, reciprocal, passive, time-invariant network is presented fully, while the relaxation of these restrictions is indicated in detail; i.e., the state-variable characterization of active, nonreciprocal, time-variable, and nonlinear networks is discussed. Finally, there is a brief guide of the current research where the state-variable analysis is brought to bear upon certain qualitative aspects of classical and nonclassical network behavior.

The constrained via minimization problem for PCB and VLSI design

A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed.<<ETX>>

Module Placement Based on Resistive Network Optimization

A new constructive placement and partitioning method based on resistive network optimization is proposed. The objective function used is the sum of the squared wire length. The method has the feature which includes fixed modules in the formulation. The overall algorithm comprises the following subprograms: optimization, scaling, relaxation, partitioning and assignment. The method is efficient because it takes advantage of net-list sparsity and has a complexity of O[n1.4 log n]. Another added special feature is that irregular-size modules within cell rows are allowed. Thus the method is particularly useful in standard-cell and gate-array designs. Experimental results on four 4K gate-array placements are illustrated, and they are far superior than manual placements.

Performance-Driven Placement of Cell Based IC's

The increasingly important role of the interconnect in the timing performance of present and future integrated circuit technologies underscores the need to reconsider conventional physical design CAD tools, and devise new ways to influence performance during layout. Interconnects are not perfect conductors, they introduce parasitic elements that load the logic gates and distort the temporal properties of the design as viewed by the logic designer. Cell placement that minimizes wirelength as the sole objective does not solve the problem, leaving a margin for performance improvement that has not been fully exploited. This paper presents a novel approach to performance-driven placement, combining timing analysis and physical design to dynamically optimize the performance of the chip during placement. The ideas are embodied in a program named Allegro, and preliminary results tested on Sea-of-Gate designs are encouraging.

PROUD: a sea-of-gates placement algorithm

An efficient method is proposed for placing modules in large and highly complex sea-of-gates chips that include preplaced I/O pads and macrocells. PROUD repeatedly solves sparse linear equations. A resistive network analogy of the placement problem and convexity of the objective function are key concepts in this algorithm. The algorithm was tested on nine real circuits. For a triple-metal-layer, 100000-gate sea-of-gate design with 26000 instances, the constructive phase took 50 minutes on a VAX 8650 and yielded excellent results for total wire length. Extensions of the method are considered.<<ETX>>

Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout

A new methodology for hierarchical floor planning and global routing for building block layout is presented. Unlike the traditional approach, which separates placement and global routing into two consecutive stages, our approach accomplishes both jobs simultaneously in a hierarchical fashion. The global routing problem is formulated at each level as a series of the minimum Steiner tree problem in a special class of partial 3-trees, which can be solved optimally in linear time. The floor planner with a maximum of five rooms per level has been implemented in the C language, running on a VAX 8650 under 4.3 BSD UNIX. The experimental results on examples with a large number of irregular blocks show that our approach out-performs other well-known deterministic algorithms, and gives results that are comparable to random-based algorithms but with a computing time an order of magnitude less. Due to the unique goal-oriented and pattern-directed features of our floor planner, it accepts specifications for overall aspect ratio and I/O pad positions, thus making our approach suitable for hierarchical design.

Performance-Driven Steiner Tree Algorithms for Global Routing

This paper presents two performance-driven Steiner tree algorithms for global routing which consider the minimization of timing delay during the tree construction as the goal. One algorithm is based on nonlinear optimization method, another uses heuristic approach to guide the construction of Steiner tree. A new timing model is established which includes both total length and critical path between source and sink in delay formulation, and an upper bound for timing delay is deducted and used to guide both algorithms. Experiment results are given to demonstrate the effectiveness of the two algorithms.

RITUAL: a performance driven placement algorithm for small cell ICs

An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described. Using sophisticated mathematical techniques, one is able to solve large problems quickly and effectively. The algorithm is very simple and elegant, making it easy to implement. In addition, it yields very good results, as is shown on a set of real examples. The algorithm was tested on the ISCAS set of logic benchmark examples using parameters for 1 mu m CMOS technology. On average , there is a 25% improvement in the wire delay for these examples compared to TimberWolf-5.6 with a small impact on the chip area.<<ETX>>