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Sunil Suresh Hatti

IBM

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Publication

Featured researches published by Sunil Suresh Hatti.

Archive | 2007

System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation

Vinod Bussa; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Rahul Sharad Moharil; Bhavani Shringari Nanjundiah

Archive | 2007

System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation

Sampan Arora; Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Chakrapani Rayadurgam

Archive | 2007

System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation

Shubhodeep Roy Choudhury; Sandip Bag; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Bhavani Shringari Nanjundiah

Archive | 2007

System and Method for Using Resource Pools and Instruction Pools for Processor Design Verification and Validation

Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Rahul Sharad Moharil

Archive | 2007

System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation

Sampan Arora; Sandip Bag; Vinod Bussa; Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Batchu Naga Venkata Satyanarayana; Shiraz Mohammad Zaman

Archive | 2007

System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation

Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Chakrapani Rayadurgam; Batchu Naga Venkata Satyanarayana

Archive | 2007

System and method for generating fast instruction and data interrupts for processor design verification and validation

Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Rahul Sharad Moharil

Archive | 2007

System and Method for Testing a Large Memory Area During Processor Design Verification and Validation

Divya S. Anvekar; Shubhodeep Roy Choudhury; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor

Archive | 2007

System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation

Sampan Arora; Divya S. Anvekar; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Bhavani Shringari Nanjundiah

Archive | 2008

SYSTEM AND METHOD FOR PREDICTING IWARX AND STWCX INSTRUCTIONS IN TEST PATTERN GENERATION AND SIMULATION FOR PROCESSOR DESIGN VERIFICATION/VALIDATION IN INTERRUPT MODE

Sampan Arora; Divya S. Anvekar; Manoj Dusanapudi; Sunil Suresh Hatti; Shakti Kapoor; Bhavani Shringari Nanjundiah

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Manoj Dusanapudi

IBM

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Shakti Kapoor

IBM

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Shubhodeep Roy Choudhury

IBM

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Rahul Sharad Moharil

IBM

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Sampan Arora

IBM

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Bhavani Shringari Nanjundiah

IBM

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Batchu Naga Venkata Satyanarayana

IBM

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Divya S. Anvekar

IBM

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Sandip Bag

IBM

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Vinod Bussa

IBM

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