Tsz Yin Man

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm2. The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV VDO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario.

Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC

The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-mum MOS technology. It is proven experimentally that the LDO provides stable voltage regulation at a variety of output-capacitor/ESR conditions and is also stable in no output capacitor condition. The preset output voltage, minimum unregulated input voltage, maximum output current at a dropout voltage of 200 mV, ground current and active chip area are 1 V, 1.2 V, 50 mA, 95 muA, and 140 mum times 320 mum, respectively. The full-load transient response in the no output capacitor case is faster than a micro second and is about 300 ns.

A 0.9-V Input Discontinuous-Conduction-Mode Boost Converter With CMOS-Control Rectifier

A 0.9-V input discontinuous-conduction-mode (DCM) boost converter delivering 2.5-V and 100-mA output is presented. A novel low-voltage pulse-width modulator is proposed. The modulator can be directly powered from the 0.9-V input instead of using the 2.5-V output as in general modulator designs. Sophisticated low-voltage analog blocks, which normally consume a large amount of power and chip area, are not required in the modulator. The impact of output-voltage ripple and transient-induced output-voltage perturbation on the operation of analog blocks inside the modulator is eliminated. Boost converter start-up sequence is also greatly simplified. A CMOS-control rectifier (CCR) is also proposed to improve converter power efficiency. The CCR is used to replace the conventional rectifying switch to provide adaptive dead-time, which helps to minimize charge-sharing loss and body-diode conduction loss. Corresponding thermal stress on the rectifying switch is hence minimized. The CCR also enables the use of small off-chip inductor and capacitor at sub-MHz switching frequency to improve light-load efficiency. This converter has been implemented in a 0.35- mum CMOS process. It is designed to operate at ~ 667 kHz with a 1 mu H inductor and 4.7 mu F output capacitor to reduce both switching loss and form factor. Experimental results prove that the converter can be directly powered from 0.9-V input with ~ 85% efficiency at 100-mA output.

CMOS-compatible zero-mask One Time Programmable (OTP) memory design

A method to design CMOS-compatible diode-based One-Time Programmable (OTP) memory is discussed in this paper. In particular the program disturb problem is resolved by using diode drivers with sufficiently high breakdown voltage. The choices of memory elements and various available diodes in a standard CMOS process are carefully studied to obtain an optimal combination. Different memory cells were fabricated in standard 0.18-¿m CMOS technology to verify the functionality of the design.

An Auto-Selectable-Frequency Pulse-Width Modulator for Buck Converters with Improved Light-Load Efficiency

In this work, an auto-selectable-frequency pulse-width modulator (ASFPWM) is introduced to enable buck converters to use compact off-chip inductors and capacitors and to minimize both the switching loss and the gate-drive loss without causing a supply-integrity problem.

A CMOS-Control Rectifier for DiscontinuousConduction Mode Switching DC-DC Converters

A sub-1V boost converter with a CMOS-control rectifier enables adaptive dead-time control and mV-range forward-voltage drop. This converter can operate with <0.9V input and deliver 2.5V and 250mW output with 85% efficiency and is intended for single-cell battery-powered mobile systems

A high-power-LED driver with power-efficient LED-current sensing circuit

For lighting application, high-power LED nowadays is driven at 350 mA and a sensing resistor is used to provide feedback for LED-current regulation. This method adds an IR drop at the output branch, and limits power efficiency as LED-current is large and keeps increasing. In this paper, a power-efficient LED-current sensing circuit is proposed. The circuit does not use any sensing resistor but extracts LED-current information from the output capacitor of the driver. The sensing circuit is implemented in a Buck-boost LED driver and has been fabricated in AMS 0.35 mum CMOS technology. Measurement results indicate a power-conversion efficiency of 92% and at least 90 times power reduction in sensing compared to existing approach.

A zero-mask one-time programmable memory array for RFID applications

A CMOS-compatible one-time programmable (OTP) memory array for RFID applications is presented. Three zero-mask antifuse (AF) devices were evaluated on their feasibility for RFID applications. Among the AFs, the gate oxide AF device can be programmed using only 7 muW of peak power and was chosen to form the RFID memory array. A memory array architecture is presented based on a compact 2-transistor cell, together with a programming circuit that does not require special high voltage transistors and consumes zero DC current during programming. The device structures were fabricated in 0.18 mum process and were experimentally verified, while circuit simulations were performed using TSMC 0.18 mum model on Cadence Analog Artist

A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure

A novel 2-bit/cell nonvolatile memory (NVM) with metal-oxide-nitride-oxide-semiconductor (MONOS) asymmetric double gate (ADG) MOSFET structure is proposed. With the double gate structure, the two conducting channels provide the ability to store 2 bits in a cell. Program and erase can be performed by channel hot electron (CHE) injection and Fowler-Nordheim (FN) tunneling respectively. The read operation and the array structure of the proposed novel NVM are also studied and described in this paper.

SOI flash memory scaling limit and design consideration based on 2-D analytical modeling

In this paper, the short-channel effect in ultrathin body (UTB) SOI Flash memory cell induced by the floating-gate is investigated by a newly developed two-dimensional analytical model. A concept of effective natural length (/spl lambda//sub eff/) is introduced as a measure of the impact of the floating-gate on the scaling limit. Even though scaling the channel thickness can significantly reduce SCE in UTB MOSFET, it becomes less effective in floating-gate device due to the floating polysilicon induced gate coupling. To minimize the floating-gate induced SCEs, the drain to floating-gate coupling has to be minimized.