Rabindra K. Roy

The Best Flip-Flops to Scan

The full-scan and the nonscan versions of a circuit This paper presents a new algorithm for selecting the best flip-flops to scan for achieving maximum fault coverage in a partial-scan circuit. The algorithm, called PASCAL (PArtial Scan AnaLysis), ranks the flip-flops based on their contribution to the fault coverage. The results of PASCAL provide a global view of the entire partial-scan design spectrum (from no scan to full scan), and allow the designer to estimate the fault coverage achievable with any number of scanned flip-flops and to select the minimal subset of flip-flops to scan for obtaining a desired fault coverage. The number of scanned flip-flops can be reduced by taking into account faults detected by functional tests.

Test compaction for sequential circuits

The authors describe a number of heuristic algorithms to compact a set of test sequences generated by a sequential circuit automatic test pattern generator (ATPG). A model has been developed and analyzed which shows that finding the optimal solution has an exponential worst-case complexity. To achieve an acceptable run time, some heuristics have been developed that yield good suboptimal solutions in a very short time. Three heuristic algorithms were developed. These algorithms were implemented in C and lex and applied to several of the ISCAS-89 benchmark sequential circuits. They reduce the test length by 17%-63% with a very small time overhead, while having little effect on the original fault overage. >

Synthesis of low power linear DSP circuits using activity metrics

Power has become an important optimizing parameter due to increasing use of portable and remote electronic systems. In a CMOS circuit, node activity is directly proportional to the amount of power drawn. We analyze activity metrics at high level for adders and multipliers and derive architectural transformations for synthesizing low power circuits. The goal is to identify data flow graph transformations that reduce overall circuit activity rather than accurate prediction of power consumption. It is shown experimentally that the transformations are power-efficient over many classes of input signals applied to several digital signal processing (DSP) test circuits.<<ETX>>

EDA challenges facing future microprocessor design

As microprocessor design progresses from tens of millions of transistors on a chip using 0.18-/spl mu/m process technology to approximately a billion transistors on a chip using 0.10-/spl mu/m and finer process technologies, the microprocessor designer faces unprecedented Electronic Design Automation (EDA) challenges over the future generations of microprocessors. This paper describes the changes in the design environment that will be necessary to develop increasingly complex microprocessors. In particular, the paper describes the current status and the future challenges along three important areas in a design flow: design correctness, performance verification and power management.

Compaction of ATPG-generated test sequences for sequential circuits

Currently available automatic test pattern generators (ATPGs) generate test sets that are nonoptimal in length. The authors describe novel heuristic techniques to reduce the length of the test set for a sequential circuit by compaction of the automatically generated patterns. Based on these techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry.<<ETX>>

Fault simulation in a distributed environment

Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<<ETX>>

Dynamic redundancy identification in automatic test generation

Test generation for combinational circuits, an NP-complete problem, shows its worst-case behavior while trying to generate tests for redundant faults and failing after an exhaustive search. The performance of an automatic test generator can be significantly improved by identifying redundancy via simple techniques which do not involve a search. The authors present a technique to identify redundant faults. This technique works dynamically during test generation, but is not based on a search process. It relies on test-covering relations among faults, which allow identification of addition redundant faults after the test generator fails to generate a test for a target fault. This technique has been implemented in AT&Ts Testpilot test generation system and has shown a reduction of up to 32% in the number of backtracks in test generation runs. >

Greedy hardware optimization for linear digital circuits using number splitting and refactorization

A greedy optimization technique for minimizing the area of linear digital systems using a combination of common subexpression elimination and modification of multiplier coefficients is proposed. Since the amount of logic required by a coefficient multiplier is dependent on the value of the coefficient, the given system is transformed, using splitting of coefficients, in such a way that the overall circuit requires a smaller area. The approach explores a much larger design space as compared to previously known techniques. The approach is the first to optimize numerically intensive digital circuits by additive decomposition of multiplier coefficients. The new synthesis scheme generates functionally equivalent but structurally different circuits with a 15 to 40% reduction in area over conventional methods, for practical circuits with DSP applications. >

Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic CMOS circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of the circuits by as much as 50%.

Synchronous test generation model for asynchronous circuits

Tests generated for asynchronous circuits using existing methods can be invalidated if the delay dependent nature and unstable states of the circuit are not considered during test generation. Test invalidation may result in a decrease in fault coverage. In this paper, we present a new method for testing asynchronous circuits. We propose a new synchronous test model (STM) that captures the essential behavior of the circuit under test. The STM has three advantages: (1) synchronous, sequential test generation techniques can be used to generate tests for the model, (2) tests generated for the STM can always be translated into tests for the circuit under test, and (3) these tests will not suffer from test invalidation due to unstable states, because the STM implicitly enforces the fundamental mode of operation during test generation. Experimental results on several benchmark show that our method generates test sets with high fault coverage and with absolutely no test invalidation. Several applications of the STM are also discussed.