Guillaume Renaud

Nonlinear acoustic resonances to probe a threaded interface

We evaluate the sensitivity of multimodal nonlinear resonance spectroscopy to torque changes in a threaded interface. Our system is comprised of a bolt progressively tightened in an aluminum plate. Different modes of the system are studied in the range 1–25 kHz, which correspond primarily to bending modes of the plate. Nonlinear parameters expressing the importance of resonance frequency and damping variations are extracted and compared to linear ones. The influence of each mode shape on the sensitivity of nonlinear parameters is discussed. Results suggest that a multimodal measurement is an appropriate and sensitive method for monitoring bolt tightening. Further, we show that the nonlinear components provide new information regarding the interface, which can be linked to different friction theories. This work has import to study of friction and to nondestructive evaluation of interfaces for widespread application and basic research.

Modeling nonlinear viscoelasticity in dynamic acoustoelasticity

Dynamic Acoustoelastic Testing (DAET) has been developed to non-invasively assess the nonlinear viscoelastic properties of fluids and solids. We propose a phenomenologically motivated model for harmonic regime to identify nonlinear viscoelastic parameters from DAET experiments. The nonlinear elastic and viscous parameters are derived from the real and imaginary components of the Taylor series expansion of the complex longitudinal modulus. The model is applied to Newtonian fluids that exhibit classical elastic nonlinearities and glass beads saturated with water that exhibit nonclassical viscoelastic nonlinearities. Hysteresis, asymmetry, and DC offset are well accounted for in the model.

Design of an on-chip stepwise ramp generator for ADC static BIST applications

This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main non-idealities affecting the linearity of the generator are discussed on a practical implementation in a 65nm CMOS technology. Electrical simulation results at transistor level are provided to verify the feasibility and performance of the proposed approach.

On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test

Linearity testing for ADCs is one of the most resource and time consuming tasks in the production test of a mixed-signal integrated system. Advanced strategies for reducing static test time, such as the reduced code linearity test technique, have been recently presented. However, the application of these techniques require a high linearity input stimulus to excite the ADC under test, which is usually provided by an external analog signal generator in the ATE. Extending the static linearity test to a BIST implementation requires to include this generator on-chip, which is a challenging task. This paper explores different possibilities for the on-chip implementation of such generators.

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator

This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutions in the order of 13 bits and 100Msps of sampling frequency.

Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs

This work presents an efficient modification of the classical servo-loop static test setup aimed at the on-chip implementation of reduced-code static linearity test techniques. The proposed modified servo-loop provides a direct measurement of the width of a given ADC code without the need of an integrated voltmeter. The proposed measurement strategy is based on using a controlled step-wise ramp stimulus generator for exciting the ADC under test in such a way that the measurement of a code width can be determined in the digital domain by simply counting the number of ramp steps between two consecutive ADC output transitions. Moreover, the ability of the proposed servo-loop to target a given ADC code makes it very suitable for implementing advanced reduced-code static test techniques. This work analyses the performance limits of the proposed discrete-time servo-loop technique and explores its application to reduced-code linearity testing of pipeline ADCs.

Design trade-offs for on-chip driving of high-speed high-performance ADCs in static BIST applications

This paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering stage, often overlooked in the literature, is in fact an essential building block for the correct functionality of the BIST in high-speed high-performance applications. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 2.5V 65nm CMOS process is presented here as demonstrator. Transistor-level simulations with a 2Vpp sinusoidal test-stimulus show an effective resolution with realistic switched-capacitor load greater than 15 bits, being a suitable solution for the static test of ADCs with effective resolutions in the order of 12 bits and 80 Msps of sampling frequency.

Probing hysteretic elasticity in weakly nonlinear materials

In this study, we propose an optimized NRUS measuring and data processing protocol dedicated to small bone samples specially designed to be used in a four-point bending mechanical fatigue test. Our goal was to assess the elastic and dissipative hysteretic nonlinear parameters repeatability with the proposed protocol using several classes of materials with weak, intermediate and high nonlinear properties. In the proposed data processing, the frequency shift Δf as a function of excitation drive amplitude is measured relatively to a reference resonance peak curve f0 (obtained at the lowest excitation level) which is repeated before each excitation drive level. Our results show that the proposed correction may be an alternative to a stringent control of temperature (which could not be achieved in this study) by increasing significantly NRUS sensitivity. With our correction procedure, we measured relative resonant frequency shifts of 10−5, which are below 10−4, often considered as the limit to NRUS sensitivity under common experimental conditions. In our experiments, we identified external temperature fluctuation as one of the major source of resonance frequency variation. A variation of 0.1°C caused a frequency variation of 0.01%, which is similar to the expected nonlinear frequency shift for weakly nonlinear materials. In the absence of correction, the data could not be interpreted to support the existence of hysteretic nonlinear behavior in bone.

Nonlinear viscoelastic measurements in fluids using “acoustical rheology”

Dynamic AcoustoElasticity (DAE) method was first developed to assess microcracks in trabecular bone tissue. However, the method appears to offer larger applications, especially in fluids, to investigate nonlinear rheological behaviors. The purpose of this work is to validate the techniques sensitivity and to characterize the viscoelasticity in fluids, and particularly in non-Newtonian fluids which exhibit complex viscoelastic properties such as shear-thinning, shear-thickening or thixotropy. DAE technique, based on the interaction of two acoustic waves (a low-frequency wave and ultrasound pulses) provides non-contact and localized measurements of viscoelastic and dissipative nonlinearities. We particularly studied several food and cosmetics products well-known for their counterintuitive behaviors. Nonlinear viscoelastic and dissipative measurements have shown strong asymmetry in tension/compression, hysteretic behavior and high level of nonlinearities.