Mao-Hsu Yen

A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications

4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROMs) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.

A three-stage one-sided rearrangeable polygonal switching network

This paper proposes a three-stage rearrangeable polygonal switching network (PSN) for interconnecting one-sided input-output terminals. In comparing our PSN with a three-stage one-sided Clos switching network of the same size and with the same number of switches, we prove that rearrangeability of a PSN is better than that of a Clos switching network. Also, the switching efficiency of the PSN is explored.

Design of a low power viterbi decoder for wireless communication applications

In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5mW at 100MHz.

Design and implementation of a low-power OFDM receiver for wireless communications

Orthogonal Frequency-Division Multiplexing (OFDM) systems can efficiently combat the issue of frequency-selective fading channels. Therefore, OFDM has become one of the most popular baseband modulation techniques for wireless communications. This paper presents the design and implementation of a low-power OFDM baseband receiver for wireless local area networks (WLAN). The proposed architecture employs low-power register files and resource-sharing techniques, thus consuming less power than many existing works. The proposed design adopts a number of area-efficient hardware structures to further reduce the hardware cost. Finally, because it is designed using 0.18 μm CMOS technology, the core of the proposed chip has approximately 239K gates, and its power consumption is approximately 36 mW at 20 MHz.

Parallel implementation of convolution encoder for software defined radio on DSP architecture

The question of how to efficiently implement bit-oriented operations such as convolutional encoding in a word-based processor platform is investigated. Our approach is to treat each word as a vector of individual bits. By reformulating a bit-oriented algorithm in vectorized format, it is shown in this work that significant speed-up of execution of such an algorithm can be achieved. Toward this goal, an efficient code generation design methodology is proposed to leverage the effort of common sub-expression elimination (CSE). The task of efficient vector-oriented code generation then becomes a pattern matching problem. The vectorization approach is demonstrated by the convolutional encoding portion of the IEEE 802.11a (WiFi) standard, implemented in C language on a Sandbridge Technologies© Inc. SB3010 baseband processor evaluation board, and more than 90% instruction cycle reduction is observed.

Design of a high-speed block interleaving/deinterleaving architecture for wireless communication applications

This paper presents a high-speed block interleaver/deinterleaver designed to prevent burst errors in wireless communications. Using FIFO banks, our proposed architecture is a high-speed design that owns lower hardware complexity and consumes lower power dissipation. Especially, the simple finite-state-machine control unit used in our design can provide an arbitrary column-wise permutation for the block interleaver.

ARAL-CR: An adaptive reasoning and learning cognitive radio platform

This paper discusses the realization of a cognitive radio (CR) reconfigurable communication architecture and platform. In particular, four key research activities are presented: (1) the design of a reasoning and learning framework for CR adaptation, (2) a software-defined radio (SDR) baseband system using GNU Radio, (3) the design of a multi-band/multi-protocol RF front-end, and (4) the design of a reconfigurable baseband transceiver.

Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System

The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size. But the design of an MCM system usually requires weeks of engineering effort, thus we need a generic MCM substrate with programmable interconnections to accelerate system prototyping. In this paper, we propose a Symmetric and Programmable MCM (SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interconnect Chips (FPICs) for substrate routing. Experimental results demonstrate that our FPIC polygonal routing module uses 12% less switches than the conventional routing module for interconnecting bare-chip slots with 84 pads. Also, experiments are conducted to determinate proper parameters for the VLSI implementation of our FPIC.

Symmetric and programmable multi-chip module for rapid prototyping system

To accelerate prototyping designs, we propose a new Symmetric and Programmable MCM (SPMCM) substrate, which consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interconnect Chips (FPICs) for substrate routing. Especially, the FPIC that we developed contains two kinds of polygonal routing modules and some virtual-wires to reduce the number of routing switches and pin count. For a bare-chip slot with 2n pads, the number of switches used in the polygonal routing module is less than the conventional routing module by /spl radic/(rF/sub C/n)/4 times, where the flexibility ratio r(F/sub C/) is close to 1.

A three-sided rearrangeable switching network for a binary fat tree

A binary fat tree needs an internal node to interconnect the left-children, right-children and parent terminals to each other. In this article, we first propose a three-stage, 3-sided rearrangeable switching network for the implementation of a binary fat tree. The main component of this 3-sided switching network (3SSN) consists of a polygonal switch block (PSB) interconnected by crossbars. With the same size and the same number of switches as our 3SSN, a three-stage, 3-sided clique-based switching network is shown to be not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters has been determined to minimise the number of switches. We derive that a rearrangeable 3-sided switching network with switches proportional to N 3/2 is most suitable to interconnect N terminals. Moreover, we propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of logic blocks interconnected by our 3SSN, such that the logic blocks in this PFPGA can be grouped into clusters to implement different logic functions. Since the programmable switches usually have high resistance and capacitance and occupy a large area, we have to consider the effect of the 3SSN structure and the granularity of its cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that the switch and speed performances are significantly improved. Based on the experimental results, we can determine the parameters of PFPGA for the VLSI implementation.