Rong Meng-tian

A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture

A design of 2-D forward and inverse integer transform processor is presented, which is suitable for MPEG-4 AVC/H.264 visual profile. The comparability between the forward and inverse transform and the symmetry of their arithmetic has been utilized in architecture. According to this design, 2-D transform is implemented by using duplicated 1-D transform. Parallel register array are used to realize the transpose operation. Under 0.35um technology, the logic gate count is only 3524 when the maximum frequency is more than 120MHz.

Crosstalk model and estimation formula for VLSI interconnect wires

We develop an interconnect crosstalk estimation model on the assumption of linearity for CMOS device. First, we analyze the terminal response of RC model on the worst condition from theS field to the time domain. The exact 3 order coefficients inS field are obtained due to the interconnect tree model. Based on this, a crosstalk peak estimation formula is presented. Unlike other crosstalk equations in the literature, this formula is only used coupled capacitance and grand capacitance as parameter. Experimental results show that, compared with the SPICE results, the estimation formulae are simple and accurate. So the model is expected to be used in such fields as layout-driven logic and high level synthesis, performance-driven floorplanning and interconnect planning.

Tradeoff design for analog integrated circuits via geometric programming

An approach of tradeoff design for analog integrated circuits is presented. Different from only one specification is optimized in traditional approach, the weighted sum of several performance specifications are objective function of optimization in this approach. Each weight factor is defined according to the specifications importance to a designer. Then the optimal solution will be the result of consideration for several performances. Analysis of weighted factors effect on optimized specifications is carried out. Hspice simulation result proves the optimization is accurate.1

An Improved Decoding Method for LDPC Codes in SC-FDE System

Single carrier transmission with cyclic prefix (SC-CP or SC-FDE), has been adopted in wireless applications as an alternative technique to orthogonal frequency division multiplexing (OFDM). In this paper, an improved decoding method for regular low density parity check (LDPC) codes is proposed to compensate for the loss in signal-to-noise (SNR) due to the CP insertion. According to our research, the algorithm to select suitable CP plays an important role in decoding. The performance of the uncoded case is well analyzed. Simulation results show that the proposed scheme is effective under both AWGN and Rayleigh fading channels.

Puncturing period on the performance of punctured turbo codes

Puncturing is the predominant strategy to construct high code rate turbo codes. Puncturing period is a crucial parameter influencing the performance of punctured turbo codes (PTC). Here we developed a new puncturing scheme of turbo codes, with which the puncturing period on the performance of PTC is studied. Consequently, suggestions on selecting the puncturing period are proposed.

A routing algorithm in WDM mesh networks with grooming capacities

Most of the work in traffic grooming has been in the area of providing efficient network designs in Wavelength division multiplexing (WDM). The objective of these traffic rooming algorithms is to reduce the cost of overall networks. In this paper, a routing algorithm based on transiently chaotic neural network is proposed to solve the problem in WDM logical topology. The objectives of the routing algorithm are accomodating all traffic requirements and using less network resource. The simulation shows that the proposed algorithm is efficient in the routing selection, meanwhile the algorithm can use less network resource.

Subspace-Based Blind Channel Estimation Method for MIMO-OFDM Systems

A subspace-based blind channel estination algo rithm for MIMO-OFDM systems is proposed. This algorithm exploits the cyclostationarity introduced by cyclic prefix of OFDM to estimate the channel parameters. The proposed new algorithm is found to be outperforming the other algorithm with respect to convergence rate and achievable mean square error and robustness to channel order over determination.

Transmission Considerations with QoS Support to Deliver Real-Time Distributed Speech Recognition Applications

Distributed speech recognition (DSR) applications have certain QoS (Quality of service) requirements in terms of latency, packet loss rate, etc. To deliver quality guaranteed DSR application over wirelined or wireless links, some QoS mechanisms should be provided. We put forward a RTP/RSVP transmission scheme with DSR-specific payload and QoS parameters by modifying the present WAP protocol stack. The simulation result shows that this scheme will provide adequate network bandwidth to keep the real-time transport of DSR data over either wirelined or wireless channels.

A VLSI implementation of a low complexity Reed-Solomon encoder and decoder for CDPD

This paper presents VLSI implementation of an area efficient 8-error correcting (63,47) Reed-Solomon(RS) encoder and decoder for the CDPD (cellular digital packet data)communication systems. We implement this RS decoder using Euclidean algorithms which are regular, simple and naturally suitable for VLSI implementation. Constant multipliers based on certain composite fields are deployed in the encoder, which significantly decreases the encoders area. Multipliers over a certain composite field GF((2)2) adopted in this paper lower the complexity of the multiplication of the decoder. The RS encoder and decoder can independently operate at a clock frequency of 30 MHz. This chip was fabricated in 0.6/spl mu/m CMOS 1P2M technology with a supply of voltage of 5V, with die area 4mm /spl times/ 4mm. The chip has been fully tested and stratifies the demand of the CDPD communication systems.