Marc Sherwin

A Four-Terminal, Inline, Chalcogenide Phase-Change RF Switch Using an Independent Resistive Heater for Thermal Actuation

An inline chalcogenide phase-change radio-frequency (RF) switch using germanium telluride and driven by an integrated, electrically isolated thin-film heater for thermal actuation has been fabricated. A voltage pulse applied to the heater terminals was used to transition the phase-change material between the crystalline and amorphous states. An ON-state resistance of 4.5 Ω (0.08 Ω-mm) with an OFF-state capacitance and resistance of 35 fF and 0.5 MΩ, respectively, were measured resulting in an RF switch cutoff frequency (Fco) of 1.0 THz and an OFF/ON resistance ratio of 105. The output third-order intercept point measured , with zero power consumption during steady-state operation, making it a nonvolatile RF switch. To the best of our knowledge, this is the first reported implementation of an RF phase change switch in a four-terminal, inline configuration.

A 10-kV Large-Area 4H-SiC Power DMOSFET With Stable Subthreshold Behavior Independent of Temperature

This paper presents the development and demonstration of large-area 10-kV 4H-SiC DMOSFETs that maintain a classically stable low-leakage normally off subthreshold characteristic when operated at les200degC. This is achieved by an additional growth (epitaxial regrowth) of a thin epitaxial layer on top of already implanted p-well regions in conjunction with a N20-based gate oxidation process. Additionally, the design space of the DMOSFET structure was explored using analytical and numerical modeling together with experimental verification. The resulting 0.15-cm2 active 0.43-cm2 die DMOSFET with 10-kV breakdown provides IDS = 8 A at a gate field of 3 MV/cm, along with a subthreshold current at VGS = 0 V that decreases from 1 muA (6.7 muA/cm2) at 25degC to 0.4 muA (2.7 muA/cm2) at 200degC.

Comparisons of Design and Yield for Large-Area 10-kV 4H-SiC DMOSFETs

Three large-area 10-kV 4H-SiC DMOSFET designs are compared with respect to their design, die area, breakdown yield, and ON-state yield. The largest of these DMOSFETs had 0.62 cm2 of active area on a 1-cm2 die, with a 10-kV device producing 40 A at a gate field of 3 MV/cm. Two designs used linear interdigitated fingers, whereas the third design used a square cell layout. The linear interdigitated finger design proved to be more robust, with higher yields than the square cell geometry. It was determined that the square cell design was yield limited due to the impact of wafer bow and total thickness variations on photolithographic accuracy, making the square cell geometry less attractive for large-area 4H-SiC DMOSFETs.

Comparison of 10 kV 4H-SiC Power MOSFETs and IGBTs for High Frequency Power Conversion

For the first time, large area 10 kV SiC power devices are being produced capable of yielding power modules for high-frequency megawatt power conversion. To this end, the switching performance and power dissipation of silicon carbide (SiC) n-channel IGBTs and MOSFETs are evaluated using numerical simulations software over an extended current range to determine the best device suitable for 10 kV applications. Each device is also optimized for minimal forward voltage drop in the on-state.

10 kV Silicon Carbide Junction Barrier Schottky Rectifier

The development of 10 kV silicon carbide (SiC) MOSFETs and Junction Barrier Schottky (JBS) diodes for application to a 13.8kV 2.7 MVA Solid State Power Substation (SSPS) is shown. The design of half-bridge power modules has extensively used simulation, from electron level device simulations to the system level trade studies, to develop the most efficient module for use in the SSPS. In the work presented within, numerical simulations and experimental results are shown to demonstrate the design and operation of 10 kV JBS diodes. It is shown that JBS diodes at 10 kV can reduce 31% of the switching losses at 20 kHz than the fastest SiC PiN diodes.

Cost Effective Integration for Millimeter Wave Phased Array Apertures

High frequency phased array apertures present significant manufacturing challenges for conventional fabrication techniques. At NGES we are working on a number of advanced integration technologies which can be utilized to reduce part count and assembly labor, resulting in more cost effective and fully capable phased array sensors. This general approach to advanced integration is not limited to a single material system (e.g. Silicon or GaAs), but is a design methodology that spans many different technologies. Looking forward to the next generation of manufacturing technologies, we see the next step beyond SoC to be SoW, or System on Wafer. Since a WaferScale system is not diced into individual die, the process inherently represents batch, parallel processing – significantly lowering fabrication costs and building off of the high geometrical accuracy of microelectronic processing. From a cost perspective, WaferScale technologies are unmatched in their parallel processing advantages enabling a more affordable cost/site metric as compared to conventional chip & wire assembly approaches.

Demonstration of 10 kV, 50A 4H-SiC DMOSFET with stable subthreshold characteristics across 25–200 °C operating temperatures

This paper has described the fabrication and demonstration of 10 kV SiC MOSFETs, with active areas of 0.15 cm2 and 0.61 cm2, capable of operating at 5-10 A and 20-50 A respectively, and demonstrating excellent, stable subthreshold characteristics as a function of operating temperature (<200 degC ). These large area SiC DMOSFETs and their promising characteristics are excellent candidates to realize high voltage high speed solid state switching applications.