Bettina Nechay

A 10-kV Large-Area 4H-SiC Power DMOSFET With Stable Subthreshold Behavior Independent of Temperature

This paper presents the development and demonstration of large-area 10-kV 4H-SiC DMOSFETs that maintain a classically stable low-leakage normally off subthreshold characteristic when operated at les200degC. This is achieved by an additional growth (epitaxial regrowth) of a thin epitaxial layer on top of already implanted p-well regions in conjunction with a N20-based gate oxidation process. Additionally, the design space of the DMOSFET structure was explored using analytical and numerical modeling together with experimental verification. The resulting 0.15-cm2 active 0.43-cm2 die DMOSFET with 10-kV breakdown provides IDS = 8 A at a gate field of 3 MV/cm, along with a subthreshold current at VGS = 0 V that decreases from 1 muA (6.7 muA/cm2) at 25degC to 0.4 muA (2.7 muA/cm2) at 200degC.

Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated Field Effect Transistor (SLCFET)

A low loss, high isolation, broadband RF switch has been developed using a novel type of field effect transistor structure that exploits the use of a super-lattice structure in combination with a three dimensional, castellated gate to achieve excellent RF switch performance. Using an AlGaN/GaN super-lattice epitaxial layer, this Super-Lattice Castellated Field Effect Transistor (SLCFET) was used to build 1-18 GHz SPDT RF switches. Measured insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35 dB of isolation and -23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.

The Super-Lattice Castellated Field Effect Transistor (SLCFET): A novel high performance Transistor topology ideal for RF switching

NGES reports the development of a novel transistor structure based on a GaN super-lattice channel with a 3D gate, named the SLCFET (Super-Lattice Castellated Field Effect Transistor). Transistor measurements provided median values of I_MAX>2.7 A/mm, V_PINCH = -8V, with R_ON=0.41 Ω-mm and C_OFF=0.19 pF/mm, for an RF switch FOM of F_CO=2.1 THz.

Single Photolithography/Implantation 120-Zone Junction Termination Extension for High-Voltage SiC Devices

The multi-zone junction termination extension (MJTE) is a widely used edge termination technique for achieving high voltage SiC devices. It is commonly implemented with multiple lithography and implantation events. In order to reduce process complexity, cycle time, and cost, a single photolithography and single implant MJTE technique has been successfully developed. The method utilizes a pattern of finely graduated oxide windows that filter the implant dose and create a graded MJTE in a single implant and single photolithography step. Based on this technique, 6 kV / 0.09 cm2 PiN diodes were fabricated utilizing a 120-zone single-implant JTE design. This novel single-implant MJTE design captures 93% of the ideal breakdown voltage and has comparable performance and yield to a baseline three implant process.

Process Tolerant Single Photolithography/Implantation 120-Zone Junction Termination Extension

The multiple-zone junction termination extension (MJTE) is a widely used SiC edge termination technique that reduces sensitivity to implantation dose variations. It is typically implemented in multiple lithography and implantation events. To reduce process complexity, cycle time, and cost, a single photolithography/implantation (P/I) MJTE technique was developed and diodes with 3-zone and 120-zone JTEs were fabricated on the same wafer. Here, the process tolerance of the single (P/I) MJTE technique is evaluated by performing CCD monitored blocking voltage measurements on diodes from the same wafer with the 3-zone and 120-zone single (P/I) JTE. The 3-zone JTE diodes exhibited catastrophic localized avalanches at the interface between the 2nd and 3rd zones due to abrupt zone transitions. Diodes with the smooth transitioning 120-zone JTE exhibited no CCD detectable avalanches in their JTE regions up to the testing limit of 12 kV. Under thick dielectric (deposited for on-wafer diode interconnection), diodes with the single P/I 3-zone JTE failed due to significant loss of high-voltage capability, while their 120-zone JTE diode counterparts were minimally affected. Overall, the single (P/I) 120-zone JTE provides a process-tolerant and robust single P/I edge termination at no additional fabrication labor.

Advances in the Super-Lattice Castellated Field Effect Transistor (SLCFET) for wideband low loss RF switching applications

The Super-Lattice Castellated Field Effect Transistor (SLCFET) uses a super-lattice in the channel region to form multiple parallel current paths in conjunction with castellations etched into that super-lattice to provide a sidewall gate structure. The sidewall gate permits the gate applied electric field to penetrate between the parallel 2DEG layers, allowing the carriers to be depleted out prior to avalanche breakdown within the material, as would occur with a conventional gate structure. Using an AlGaN/GaN super-lattice, we report on this method as a way to scale RF switch performance, decreasing ON resistance without significantly increasing OFF capacitance, with a median measured ON resistance of 0.38 Ω-mm and a median measured OFF capacitance of 0.21 pF/mm, leading to an RF switch figure of merit, FCO=2.0 THz. 90/10 and 10/90 fall and rise times for the SLCFET have been measured to be faster than 100 nsec, while the RF power handling for a series SLCFET has been measured at 10 GHz to be greater than 10 W without loss compression. Wideband SPDT RF switch performance over a 0.5-20 GHz bandwidth with <;|-0.3| dB of insertion loss and >|-30| dB of isolation has been achieved.

11.72 cm2 SiC Wafer-Scale Interconnected 1.8 kV / 64 kA PiN Diode

To meet the large current handling requirements of modern power conditioning systems, paralleling of a large number of devices is required. This increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these complexities, PiN diodes were designed, fabricated at high yields, tested, and interconnected on a three-inch 4H-SiC wafer to form an 11.72 cm2 wafer-scale diode. The wafer-scale diode exhibited a breakdown voltage of 1790 V at an extremely low leakage current density of less than 0.002 mA/cm2. Under pulsed conditions, the peak current through the wafer-scale diode is 64.3 kA with a forward voltage drop of 10.3 V. The dissipated energy was 382 J and the action exceeded 1.7 MA2-sec.

High-Yield 4H-SiC Thyristors for Wafer-Scale Interconnection

Modern power conditioning systems require large active area devices which can support high currents. Though the breakdown and thermal properties of SiC make it an excellent choice for power switching applications, active area size is currently limited due to material and processing defects. One alternative is to parallel discrete diced die to achieve large active areas. However, this increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these issues and achieve devices of high current switching capabilities, thyristors were designed and fabricated for the purpose of wafer-scale interconnection - which avoids the need of dicing and bonding and can achieve significant current density improvement over the paralleled diced device approach. Discrete thyristors fabricated for interconnection exhibited excellent yields and good uniformity of both blocking and on-state characteristics, showing great promise for large-scale interconnection.

Electron emission from silicon tip arrays controlled by np junction minority carrier injection

The authors demonstrate for the first time the injection of electrons across an n-type to p-type silicon junction and their subsequent tunneling from approximately 1 μm tall p-type silicon points into a vacuum gap. The diffusive flow of these minority carriers in the p-type material is controlled by the application of a bias voltage in the form of a base contact metallization contact on the p-type silicon, in analogy with a bipolar junction transistor. Using an array density of 4×106 tips/cm2, the authors measured a maximum average current of 1 nA per tip. Increasing the base contact bias voltage from 0 to ∼1 V changes the emission from a supply limited regime typically observed with p-type silicon emitters, bringing the emitted current back to a linear Fowler–Nordheim characteristic similar to that observed previously by photon generation of carriers in p-type silicon tips. The authors finally note that in our short tips, minority carrier flow should be a nondissipative largely adiabatic diffusive transp...

High-Performance SLCFETs for Switched Filter Applications

FET-based switched filters do not occupy a large space in the literature due to the high loss of the switches relative to other technologies. The Super-Lattice Castellated Field Effect Transistor (SLCFET) is a low loss, high isolation, broadband RF switch that meets this need. A 4 channel tunable band pass filter employing SLCFET switches in a splitter/combiner network was fabricated in order to demonstrate the enabling capability of the SLCFET for this application. Each filter state employed a novel, high-Q LC circuit. The insertion loss of the MMIC passbands was around -6.5 dB, of which -1.3 dB was attributable to the six Single Pole Double Throw (SPDT) switches in the network. Breakout SPDTs were measured from 0.5 to 25 GHz. Measured insertion loss at 18 GHz was -0.41 ± 0.1 dB and isolation was -28.8 ± 0.1 dB, for 35 SPDTs on the wafer.