Marcel Mitran

A framework for reducing instruction scheduling overhead in dynamic compilers

Start-up time is a serious concern for high-availability applications such as web servers, transaction managers, and batch processes. Compilation time contributes directly to start-up costs in dynamic compilers. Up to 30% of compilation time is spent scheduling instructions in the IBM® Testarossa just-in-time compiler. In this paper, we describe a scheduling framework that reduces scheduling overhead by up to 61% with little to no degradation in throughput performance. By combining online profile-directed feedback data with information generated during register allocation, our framework identifies code regions that will benefit most from instruction scheduling. We evaluate our framework on typical client-side applications, multi-threaded server applications to production application servers on the IBM® zSeries® 990 and POWER#8482; platforms.

Mining opportunities for code improvement in a just-in-time compiler

The productivity of a compiler development team depends on its ability not only to the design effective solutions to known code generation problems, but also to uncover potential code improvement opportunities. This paper describes a data mining tool that can be used to identify such opportunities based on a combination of hardware-profiling data and on compiler-generated counters. This data is combined into an Execution Flow Graph (EFG) and then FlowGSP, a new data mining algorithm, finds sequences of attributes associated with subpaths of the EFG. Many examples of important opportunities for code improvement in the IBM® Testarossa compiler are described to illustrate the usefulness of this data mining technique. This mining tool is specially useful for programs whose execution is not dominated by a small set of frequently executed loops. Information about the amount of space and time required to run the mining tool are also provided. In comparison with manual search through the data, the mining tool saved a significant amount of compiler development time and effort.

Performance innovation in the IBM zEnterprise 196 processor

The IBM zEnterprise® 196 achieves substantial performance gains over prior designs across the full spectrum of workloads being run on todays enterprise information technology systems, ranging from large data-intensive transaction processing workloads to central processing unit-intensive business applications. Each of these required innovations in the design of the hardware, software, and instruction-set architecture (ISA) with performance gains coming from several sources: the out-of-order microprocessor core design, the multilevel cache structure, new ISA facilities, and additional ISA extensions to enable efficient scaling of large multiprocessor operating system images. These enhancements were achieved through collaborative development among hardware, software, compiler, architecture, and performance analysis teams. This paper describes the performance contributions from these sources, with particular focus on the new architectural facilities.