Marcelo Götz

TOWARDS RUN-TIME PARTITIONING OF A REAL TIME OPERATING SYSTEM FOR RECONFIGURABLE SYSTEMS ON CHIP

Reconfigurable computing have successfully been designed taking into advantage the supporting of architectures based on the FPGAs and CPU. Moreover, the new hybrid FPGAs (e.g. Virtex-II Pro™), provides a hardcore general-purpose processor (GPP) embedded into a field of programmable gate arrays. Together with the ability to be partially reconfigured, those chips are very attractive for implementation of run-time reconfigurable embedded systems. However, most of the efforts in this field were made in order to apply these capabilities at application level, leaving to the Operating System (OS) the provision of the necessary mechanisms to support these applications. This paper present an approach for run-time reconfigurable Operating System, which take advantage of the new hybrid FPGA chips to reconfigure itself based on online estimation of application demands. The paper focus on run-time assignment and reconfiguration of OS services over a hybrid architecture. The proposed model uses a 0-1 Integer programming strategy for assigning OS components over a hybrid architecture, as well as an alternative heuristic algorithm for it. In addition, the evaluation of the reconfiguration costs are presented and discussed.

Deterministic Mechanism for Run-time Reconfiguration Activities in an RTOS

Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and field programmable gate array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of todays embedded systems. However, the relative high reconfiguration costs often are an obstacle when using such architectures for run-time reconfigurable systems. In order to still be able to benefit from the flexibility of such systems, the used real-time operating system must explicitly respect the reconfiguration time. In such systems, the reconfiguration activities need to be carried out during run-time without causing critical applications to miss their deadlines. In this paper, we show how we model these reconfiguration activities as aperiodic jobs. Therefore, we apply the server-based method from the real-time scheduling theory to the scheduling of aperiodic activities. Using these techniques, we can achieve a deterministic environment for reconfiguration activities as well as an improvement of their responsiveness.

(Re-) configurable real-time operating systems and their applications

There are trends in the area of real-time computing to shift from RTOS kernels (fixed or configurable ones) to more flexible approaches, where a RTOS (real-time operating system) is generated exactly in the way it is needed for a specific application context. One example for this approach is the component library Dreams, developed at HNI of Universitat Paderborn. This library offers a fine granular set of components that can be customized at source code level and configured in a very flexible way. The needed configurator, also developed at HNI, is called TEReCS. It allows mapping specific application needs exactly onto the needed and properly customized stet of Dreams component. The available hardware resources are taken into consideration as well. In this paper, we describe how this potential has been used or can be used for rather different classes of applications. The three application examples considered origin from the control of flexible manufacturing systems, synthesis of distributed embedded software, and the real-time image processing needed to offer virtual camera positions in broadcasting sports events. In the first application example, it is discussed how the control of flexible manufacturing systems (so-called holonic approach) can be interpreted as a special kind of a ROTS and which configuration needs have to be considered. In the second example, a model of distributed embedded systems by means of hierarchical predicate/transition nets (a special kind of higher order Petri nets) is directly transformed into a specially configured RTOS. Finally, in the third example, a very special application is considered. From a fixed camera position at known locations, the image that would be produced by a camera position at an arbitrary location (virtual camera) is calculated. This application is intended for sports events like soccer matches. As this, obviously, has to happen in real-time, sophisticated support by a properly tailored RTOS running on processor clusters has to be provided. For this application we decided to configure RTAI Linux in a proper way.

Run-time reconfigurable RTOS for reconfigurable systems-on-chip

High computational performance and flexibility are the requirements of nowadays embedded systems and they are increasing constantly. Moreover, a single architecture must be able to support different applications with dynamically requirements (changing environments). Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and Field Programmable Gate Array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of todays embedded systems. As an Operating System (OS) is desired to provide support for such systems, it has to use the available resources in an optimal way (competing with the application), since an embedded system architecture usually lack of resources. Therefore, we present here our approach towards a reconfigurable RTOS that is able to distribute itself over a hybrid architecture (comprising FPGA and CPU). In this work we will present the main concepts and methods used to achieve the desired RTOS. Moreover, we present some preliminary evaluation results which show the applicability of our approach.

Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems

When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and design methods are required. Such methods must respect the whole range of functionality of the reconfigurable fabrics. In particular, the heterogeneity and reconfiguration delay of modern FPGAs are important details. Comprehensive methods to exploit these characteristics within the integrated design of embedded systems are still not available. In this paper, we introduce a synthesis methodology for reconfigurable systems that respects the specific requirements of run-time reconfiguration. The methodology bases on profound concepts, and expands known notations and model techniques.

Tool support for evaluating temporal characteristics of industrial protocols

In fieldbus automation systems, the correctness of the real time behavior depends not only on the intra-device processing and process scheduling, but also on the inter-device communication that exchanges process variables information. The article presents a tool to evaluate temporal characteristics of industrial communication protocols. It can monitor runtime timing requirements of proposed communication, according to variable conditions affecting the communication, and present graphically time characteristics of the resulting validation. Two case studies, one evaluating the real time characteristics of the Foundation Fieldbus protocol and another one evaluating timing characteristics of the CSMA medium access protocol used are presented in order to validate the features of the presented tool.

Reconfigurable Microkernel-based RTOS: Mechanisms and Methods for Run-Time Reconfiguration

The requirements of high computational performance and flexibility of the contemporary embedded systems are continuously increasing. Moreover, a single architecture must be able to support different applications with dynamical requirements (changing environments). Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and field programmable gate array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of todays embedded systems. An operating system (OS), which is desired to provide support for such systems, has to use the available resources in an optimal way (competing with the applications), since embedded system architectures are usually lacking in resources. In this paper, we present our approach towards a reconfigurable RTOS that is able to distribute itself over a hybrid architecture (comprising FPGA and CPU). We describe the main concepts and methods used to achieve the desired RTOS. Moreover, we present some preliminary evaluation results which show the realizability of our approach

Applying single processor algorithms to schedule tasks on reconfigurable devices respecting reconfiguration times

In the single machine environment, several scheduling algorithms exist that allow to quantify schedules with respect to feasibility, optimality, etc. In contrast, reconfigurable devices execute tasks in parallel, which intentionally collides with the single machine principle and seems to require new methods and evaluation strategies for scheduling. However, the reconfiguration phases of adaptable architectures usually take place sequentially. Run-time adaptation is realized using an exclusive port, which is occupied for some reasonable time during reconfiguration. Thus, we can find an analogy to the single machine environment. In this paper, we investigate the appliance of single processor scheduling algorithms to task reconfiguration on reconfigurable systems. We determine necessary adaptations and propose methods to evaluate the scheduling algorithms.

A run-time partitioning algorithm for RTOS on reconfigurable hardware

In today’s system design, reconfigurable computing plays more and more an important role. By the extension of reconfigurable devices like FPGAs with one or more CPUs new challenges in system design should be solved. These new hybrid FPGAs (e.g. Virtex-II ProTM), provides a hardcore general-purpose processor (GPP) embedded into a field of programmable gate arrays. Furthermore, they offer partial reconfiguration. Therefore, those hybrid FPGAs are very attractive for implementation of run-time reconfigurable embedded systems. However, most of the efforts in this field were made in order to apply these capabilities at application level, leaving to the Operating System (OS) the provision of the necessary mechanisms to support these applications. In this paper, an approach for run-time reconfigurable Operating System, which takes advantage of the new hybrid FPGAs to reconfigure itself based on online estimation of application demands, is presented. Especially run-time assignment and reconfiguration of OS services over hybrid architecture are discussed. The proposed model uses a 0-1 Integer programming strategy for assigning OS components over hybrid architecture, as well as an alternative heuristic algorithm for it. Furthermore, the evaluation of the reconfiguration costs are presented and discussed.

Embedded Systems: Design, Analysis and Verification

This paper presents a hardware/software (HW/SW) codesign framework (TECSCE) which enables software developers to easily design complex embedded systems such as massive data-parallel systems. TECSCE is implemented by integrating TECS and SCE: TECS is a component technology for embedded software, and SCE provides an environment for system-on-a-chip designs. Since TECS is based on standard C language, it allows the developers to start the design process easily and fast. SCE is a rapid design exploration tool capable of efficient MPSoC implementation. TECSCE utilizes all these advantages since it supports transformation from component descriptions and component sources to SpecC specification, and lets the developers decide data partitioning and parallelization at a software component level. Moreover, TECSCE effectively duplicates software components, depending on their degree of data parallelizing, to generate multiple SpecC specification models. An application for creating a panoramic image removing objects, such as people, is illustrated as a case study. The evaluation of the case study demonstrates the effectiveness of the proposed framework.