Florian Dittmann

Deterministic Mechanism for Run-time Reconfiguration Activities in an RTOS

Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and field programmable gate array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of todays embedded systems. However, the relative high reconfiguration costs often are an obstacle when using such architectures for run-time reconfigurable systems. In order to still be able to benefit from the flexibility of such systems, the used real-time operating system must explicitly respect the reconfiguration time. In such systems, the reconfiguration activities need to be carried out during run-time without causing critical applications to miss their deadlines. In this paper, we show how we model these reconfiguration activities as aperiodic jobs. Therefore, we apply the server-based method from the real-time scheduling theory to the scheduling of aperiodic activities. Using these techniques, we can achieve a deterministic environment for reconfiguration activities as well as an improvement of their responsiveness.

Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems

When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and design methods are required. Such methods must respect the whole range of functionality of the reconfigurable fabrics. In particular, the heterogeneity and reconfiguration delay of modern FPGAs are important details. Comprehensive methods to exploit these characteristics within the integrated design of embedded systems are still not available. In this paper, we introduce a synthesis methodology for reconfigurable systems that respects the specific requirements of run-time reconfiguration. The methodology bases on profound concepts, and expands known notations and model techniques.

Towards a high-level synthesis of reconfigurable bit-serial architectures

This paper presents high-level synthesis methods for a fully reconfigurable self-timed synchronous bit-serial pipeline architecture. The idea is to distribute the central control unit. Local controls of the operators are realized through a one-shot implementation of the central control engine. Specialized routing components allow the reconfiguration of the implemented circuit with respect to rapid system prototyping. We describe several kinds of high-level synthesis approaches, especially the scheduling, which can be used for this type of architecture. This means we optimize specific characteristics, like loops, junctions and splitters, during the synthesis phase.

Algorithmic skeletons for the programming of reconfigurable systems

Reconfigurable hardware such as FPGAs combines performance and flexibility, two inherent requirements of many modern electronic devices. Moreover, using reconfigurable devices, time to market can be reduced while simultaneously cutting the costs. However, the design of systems that beneficially explore the reconfiguration capabilities of modern FPGAs is cumbersome and little automated. In this work, a new approach is described that starts from a very high level of abstraction, so-called algorithmic skeletons, and exploits the additional information of this level of abstraction to beneficially execute on reconfigurable devices. Particularly, the approach focuses on dynamic run-time reconfiguration on partially reconfigurable FPGAs. As a first introduction to this approach, we consider stream parallelism paradigms including their composition.

Caching in Real-Time Reconfiguration Port Scheduling

In reconfigurable systems, the concept of caching configurations can be employed to reduce the reconfiguration overhead, as already loaded configurations can be reused. In case reconfigurable systems are resources for real-time systems, caching may even improve schedulability, as tasks can be executed immediately. The real-time reconfiguration port scheduling of this work combines mono processor scheduling algorithms and parallel slot execution, which particularly allows us to benefit from caching. However, a comprehensive design of methods is required. We discuss concepts for introducing caching to this new way of real-time scheduling on partially reconfigurable devices.

Invariants for distributed local control elements of new synchronous bit-serial architecture

The growing need for application class specific but still flexible data processing leads to a demand of new computer architectures. Reorganization and combination of proven design paradigms are promising ways to reach these goals. The fully re-configurable self-timed bit-serial and fully interlocked MACT architecture is one of those new architectures. Although MACT does not rely on a central controller, its local synchronization still demands special care is taken. This fact is especially true if routers are added to the architecture. In this paper we present fundamental invariants for the high level synthesis of MACT as well as an extended explanation of the routing elements. We prove the usefulness of the architecture by an example implementation of two convolution filters within one dataflow graph.

Dynamic relocation of hybrid tasks: Strategies and methodologies

Reconfiguration-based architectures are increasingly gaining attention of designers due to their benefits of flexibility, re-programmability and high computational performance. The combination of general purpose processors and reconfigurable fabrics (e.g., FPGAs), may provide those valuable characteristics, which are becoming essential for modern and future embedded systems. Such hybrid systems permit the existence of hardware tasks, which shall be properly managed by the operating system, thus allowing for their coexistence with software tasks. Nevertheless, in order to completely exploit this feature, the operating system must be capable of relocating a task between hardware and software execution domains. Runtime relocation of tasks (including preemption and resumption) between two devices following different computation paradigms (parallel vs. instruction based) however is a challenging job. In this work we propose a comprehensive and embracing methodology, which starts from a unified task representation, and goes to the final implementation of such hybrid tasks. For its accomplishment, a framework is proposed to help the user in designing a hybrid task, which also generates automatically the underlying infrastructure that is in charge of performing the dynamic relocation of a hybrid task. In order to prove the applicability of our concept and the efficiency of our framework, a case study is presented including its results.

Reconfigurable Microkernel-based RTOS: Mechanisms and Methods for Run-Time Reconfiguration

The requirements of high computational performance and flexibility of the contemporary embedded systems are continuously increasing. Moreover, a single architecture must be able to support different applications with dynamical requirements (changing environments). Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and field programmable gate array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of todays embedded systems. An operating system (OS), which is desired to provide support for such systems, has to use the available resources in an optimal way (competing with the applications), since embedded system architectures are usually lacking in resources. In this paper, we present our approach towards a reconfigurable RTOS that is able to distribute itself over a hybrid architecture (comprising FPGA and CPU). We describe the main concepts and methods used to achieve the desired RTOS. Moreover, we present some preliminary evaluation results which show the realizability of our approach

Placement of intermodule connections on partially reconfigurable devices

This paper presents algorithms for the placement of intermodule signals on dynamically and partially reconfigurable devices. Intermodule signals facilitate communication across reconfigurable module boundaries on FPGA devices and must guarantee conformance to partial reconfiguration requirements, i.e., they must represent static and fixed communication resources. Beside the realization of such communication as reliable signals, the physical location must be conform to all possible abutting modules, particularly if different modules with different communication requirements are temporally loaded into the same physical location. In this paper, we investigate the requirements for the placement of signals for such temporal changing conditions. After presenting and categorizing critical scenarios, we formalize strategies to find valid locations for the intermodule signals. Considering the dynamically loadable modules and their connections as a graph, we can avoid signal conflicts, if the physical allocation of the signals harmonizes with all modules in the nearest and second nearest neighboring range. In order to prove the applicability, we test our developed algorithms for different scenarios

Applying single processor algorithms to schedule tasks on reconfigurable devices respecting reconfiguration times

In the single machine environment, several scheduling algorithms exist that allow to quantify schedules with respect to feasibility, optimality, etc. In contrast, reconfigurable devices execute tasks in parallel, which intentionally collides with the single machine principle and seems to require new methods and evaluation strategies for scheduling. However, the reconfiguration phases of adaptable architectures usually take place sequentially. Run-time adaptation is realized using an exclusive port, which is occupied for some reasonable time during reconfiguration. Thus, we can find an analogy to the single machine environment. In this paper, we investigate the appliance of single processor scheduling algorithms to task reconfiguration on reconfigurable systems. We determine necessary adaptations and propose methods to evaluate the scheduling algorithms.