Marcelo Yuffe

The Implementation of the 65nm Dual-Core 64b Merom Processor

Merom is a dual-core 64b processor implementing the Coretrade architecture. The 143mm2 die has 291M transistors in a 65nm 8M process. The shared 4MB 16-way L2 cache uses PMOS power gating to minimize leakage. The processor operates in a wide core frequency range of 1 to 3GHz, a bus frequency range of 666 to 1333MHz and voltage range of 0.85 to 1.325V, while providing 40% better power performance.

A fully integrated multi-CPU, GPU and memory controller 32nm processor

This paper describes the 32nm Sandy Bridge processor that integrates up to 4 high performance Intel Architecture (IA) cores, a power/performance optimized graphic processing unit (GPU) and memory and PCIe controllers in the same die. The Sandy Bridge architecture block diagram is shown in Fig. 15.1.1 and the floorplan of a four IA-core version is shown in Fig. 15.1.2. The Sandy Bridge IA core implements an improved branch prediction algorithm, a micro-operation (Uop) cache, a floating point Advanced Vector Extension (AVX), a second load port in the L1 cache and bigger register files in the out-of-order part of the machine; all these architecture improvements boost the IA core performance without increasing the thermal power dissipation envelope or the average power consumption (to preserve battery life in mobile systems). The CPUs and GPU share the same 8MB level-3 cache memory. The data flow is optimized by a high performance on die interconnect fabric (called “ring”) that connects between the CPUs, the GPU, the L3 cache and the system agent (SA) unit that houses a 1600MT/s, dual channel DDR3 memory controller, a 20-lane PCIe gen2 controller, a two parallel pipe display engine, the power management control unit and the testability logic. An on die EPROM is used for configurability and yield optimization.

A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor

This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the on-die thermal sensors, and a novel debug port.

4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance

Intels 6th generation Core processor (code named “Skylake” or SKL) was designed to enable PC performance and user-experience at smaller and thinner form factors and enable fan-less PC platforms. It required optimization to an extremely low thermal design point (TDP). The lower average power consumption of SKL vs. the previous generation considerably increases the system battery life and allows full-day battery life or thinner designs with smaller batteries. The SKL product family is manufactured using an Intel 14nm tri-gate CMOS 11-metal-layer technology, as with the previous Core generation. Different dice include: 2 or 4 cores, a shared last-level cache (LLC, 1MB/core), a scalable graphic processor (GP) with 24, 48 or 72 execution units (EU), an image processing unit (IPU, supporting 4 cameras simultaneously), 2 channels of DDR3/LPDDR3/DDR4, a display engine (DE) and 3 display IO ports configurable to eDP, DP or HDMI. In mobile SKUs, the peripheral control hub (PCH) resides in the same package (MCP) as the CPU and communicates through an on-package IO (OPIO) bus. For desktop (DT), the PCH resides on the platform. Fig. 4.1.1 presents the SKL block diagram for the minimum configuration (2 cores, 24 EU GP, MCP). A key challenge was the need to add new capabilities, while reducing power, especially for some of the popular uses (media, casual gaming, speech recognition and advanced imaging).

The Second Generation Intel® Core™: A highly integrated high performance multi IA-core and processor graphics chip

This paper describes the Second Generation Intel® Core™ processor, a 32nm monolithic die integrating four IA cores, a processor graphics and a memory controller. The die was designed for high performance but without compromising the part power consumption or the part and system cost. To achieve these targets a modular design methodology was devised, this methodology allows fast configuration of the die to achieve the optimal performance/cost/power point for a specific market segment. In this paper some of the techniques used to control the die and package cost are described. Special attention is given to debug-ability hooks that considerably reduce the system time-to-market of this kind of highly integrated processors.