Marcio Merino Fernandes

ARCHITECT-R: a system for reconfigurable robots design

An increasing interest in the design of mobile robots has been observed in recent years, which is mainly motivated by technological advances that may allow their application to consumer markets, in addition to industrial areas.Although sophisticated techniques have been developed, choosing the appropriate hardware-software partitioning and programming robot functions are still very complex tasks.Current approaches often involve the design and implementation of hardwired solutions, with the associated problems of a long development cycle and inflexibility.In this paper we present a framework called ARCHITECT-R, which aims to design and program specialized hardware for robots based on FPGAs. We also present the first results obtained using this framework.

A Mersenne Twister Hardware Implementation for the Monte Carlo Localization Algorithm

Mobile robot localization is the problem of estimating a robot position based on sensor data and a map of the environment. One of the most used methods to address this problem is based on the Monte Carlo Localization (MCL) algorithm, which is a sample based state estimation that offers some advantages over the traditional Gaussian method. This work presents an embedded system based on an FPGA (Field-Programmable Gate Array), customized to compute the complete MCL algorithm in a response time compatible with real mobile robot applications. At the core of the system is the Mersenne Twister pseudo-random number generator, used to spread random particles over the robot navigation map. Experimental results have shown that the proposed hardware architecture is able to generate 125M numbers of 32bits/sec and that for 1k features each MCL iteration takes 0.27 sec. Additionally, this paper provides some evidences about the impact caused by the choice of random number generator on the MCL algorithm convergence speed.

LALP: A Language to Program Custom FPGA-Based Acceleration Engines

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained with Application-Specific Integrated Circuits, while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers in order to master hardware description languages (HDLs) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Bearing in mind an FPGA available resources, it has been developed LALP (Language for Aggressive Loop Pipelining), a novel language to program FPGA-based accelerators, and its compilation framework, including mapping capabilities. The main ideas behind LALP are to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to allow the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. Those features are particularly useful to implement loop pipelining, a well regarded technique used to accelerate computations in several application domains. This paper describes LALP, and shows how it can be used to achieve high-performance computing solutions.

LALP: A Novel Language to Program Custom FPGA-Based Architectures

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers and to master hardware description languages (HDLs) such as VHDL or Verilog. The attempts to furnish a high-level compilation flow (e.g., from C programs) still have open issues before efficient and consistent results can be obtained. Bearing in mind the FPGA resources, we have developed LALP, a novel language to program FPGAs. A compilation framework including mapping capabilities supports the language. The main ideas behind LALP is to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to permit the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. In this paper we describe LALP, and show how it can be used to achieve high-performance computing solutions.

On using LALP to map an audio encoder/decoder on FPGAs

This paper presents the use of LALP to implement typical industrial application kernels, ADPCM Encoder and Decoder, in FPGAs. LALP is a domain specific language and its compilation framework aims to the direct mapping of algorithms originally described in a high-level language onto FPGAs. In particular, LALP focuses on loop pipelining, a key technique for the design of hardware accelerators. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware. We present experimental results showing significant performance gains using this approach, while still keeping the language syntax and semantics close to popular high level software languages, a desirable feature when considering time to market constraints. We believe the performance gains observed for the ADPCM implementation can be extended to other industrial applications relying on algorithms spending most of their execution time on loop structures, such signal and image processing.

Automatic generation of FPGA hardware accelerators using a domain specific language

This paper describes an alternative approach to direct mapping loops described in high-level languages onto FPGAs. Different from other approaches, this technique does not inherit from software pipelining techniques. The control is distributed over operations, thus a finite state machine is not necessary to control the order of operations, allowing efficient hardware implementations. The specification of a hardware block is done by means of LALP, a domain specific language specially designed to help the application of the techniques. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware blocks.

Practical education fostered by research projects in an embedded systems course

The very nature of universities makes them unique environments for research and teaching. Although both activities constantly borrow from each other, a deeper level of interaction is not always achieved for several reasons. This paper presents a successful experience on conducting an undergraduate course on embedded systems, based on strong interaction with related research activities previously conducted by the authors. Known for being everywhere, embedded systems are constantly expanding in both complexity and volume production. In addition, heterogeneous systems are becoming prevalent in modern applications, standing as an additional difficulty to students in this area. In this context, this paper presents experiences in teaching embedded systems using a project-based learning pedagogical approach, with strong emphasis on mobile robotic applications previously developed by MSc and PhD students. As a result, it has been observed that undergraduate students have the opportunity to build a strong background and feel better prepared to face the challenges to be found in their future professional activities.

Teaching embedded systems with FPGAs throughout a computer science course

Although embedded systems have been around for quite a long time, just in recent years they have attracted major industry and academic interest. There is a perception that a computing paradigm shift is taking place, and so the need to provide computer science students with the required expertise in the field. In this paper we describe our experience of using a reconfigurable computing platform throughout a number of courses. By doing so we allow students to get acquired to embedded systems concepts and practices under different contexts in the normal curriculum. The application of this strategy have allowed considerable gains for students taking embedded system courses, research projects in the field, and also professional activities.

SeMiner: A Flexible Sequence Miner Method to Forecast Solar Time Series

X-rays emitted by the Sun can damage electronic devices of spaceships, satellites, positioning systems and electricity distribution grids. Thus, the forecasting of solar X-rays is needed to warn organizations and mitigate undesirable effects. Traditional mining classification methods categorize observations into labels, and we aim to extend this approach to predict future X-ray levels. Therefore, we developed the “SeMiner” method, which allows the prediction of future events. “SeMiner” processes X-rays into sequences employing a new algorithm called “Series-to-Sequence” (SS). It employs a sliding window approach configured by a specialist. Then, the sequences are submitted to a classifier to generate a model that predicts X-ray levels. An optimized version of “SS” was also developed using parallelization techniques and Graphical Processing Units, in order to speed up the entire forecasting process. The obtained results indicate that “SeMiner” is well-suited to predict solar X-rays and solar flares within the defined time range. It reached more than 90% of accuracy for a 2-day forecast, and more than 80% of True Positive (TPR) and True Negative (TNR) rates predicting X-ray levels. It also reached an accuracy of 72.7%, with a TPR of 70.9% and TNR of 79.7% when predicting solar flares. Moreover, the optimized version of “SS” proved to be 4.36 faster than its initial version.

An Optimized Data Mining Method to Support Solar Flare Forecast

Historical Solar X-rays time series are employed to track solar activity and solar flares. High level of X-rays released during Solar Flares can interfere in telecommunication equipment operation. In this sense, it is important the development of computational methods to forecast Solar Flares analyzing the X-ray emissions. In this work, historical Solar X-rays time series sequences are employed to predict future Solar Flares using traditional classification algorithms. However, for large data sequences, the classification algorithms face the problem of “dimensionality curse”, where the algorithms performance and accuracy degrade with the increase in the sequence size. To deal with this problem, we proposed a method that employs feature selection to determine which time instants of a sequence should be considered by the mining process, reducing the processing time and increasing the accuracy of the mining process. Moreover, the proposed method also determines which are the antecedent time instants that most affect a future Solar Flare.