Ricardo Menotti

A Methodology to Design FPGA-based PID Controllers

This paper presents a methodology to implement PID (proportional, integral, derivative) controllers in FPGAs (field-programmable gate arrays) using fixed-point numerical representation. The Matlab/Simulink environment is used for modeling, simulation and evaluation the performance provided by different fixed-point representations using a given control process. A static bit-width analyzer is used to give a specialized fixed-point representation for each operand/operator in the controller system. After bit-width analysis, a VHDL representation of the system is generated. Results show that the proposed methodology leads to shorten design cycles achieving important resource savings by employing specialized fixed-point representations.

Aggressive Loop Pipelining for Reconfigurable Architectures

In this work aims new techniques for mapping software loops to FPGAs. Extensive and aggressive use of pipelining techniques for achieving high performance solutions is the main goal. Those techniques are foreseen to effectively take advantage of the hardware synergies available in the current FPGA devices, especially the DSP blocks and the on-chip configurable memories.

Characterisation of Challenges for Testing of Adaptive Systems

Context: Exercising the implementation of an adaptive system (AS) effectively, in order to detect faults, is not a trivial task. This is due to characteristics of this type of systems, such as the high number of configurations and runtime adaptations. In this context, the characterisation of challenges for testing ASs may support the definition of suitable testing strategies. However, such characterisation is currently spread over several studies in the literature. Objective: analysing testing-related challenges for ASs which are described in the literature, and establishing a generic classification. Method: we extended a Systematic Literature Review (SLR) of studies that address challenges for AS testing. By analysing the combined results (original and extended), we mapped descriptions found in individual studies, based on their similarities, in order to create a list of generic challenges. Results: a list of 12 generic challenges based on 34 specific ones described by several authors. Additionally, we analysed the relationship between the challenges and inherent properties of ASs. Conclusion: different terminology, varied levels of details and particular contexts (e.g. specific AS implementations) are recurring problems related to the characterisation of challenges for testing ASs. Generalisations such as the one proposed in this work may help researchers and practitioners do devise customised testing strategies that focus in recurring, inherent properties of ASs.

LALP: A Language to Program Custom FPGA-Based Acceleration Engines

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained with Application-Specific Integrated Circuits, while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers in order to master hardware description languages (HDLs) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Bearing in mind an FPGA available resources, it has been developed LALP (Language for Aggressive Loop Pipelining), a novel language to program FPGA-based accelerators, and its compilation framework, including mapping capabilities. The main ideas behind LALP are to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to allow the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. Those features are particularly useful to implement loop pipelining, a well regarded technique used to accelerate computations in several application domains. This paper describes LALP, and shows how it can be used to achieve high-performance computing solutions.

LALP: A Novel Language to Program Custom FPGA-Based Architectures

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers and to master hardware description languages (HDLs) such as VHDL or Verilog. The attempts to furnish a high-level compilation flow (e.g., from C programs) still have open issues before efficient and consistent results can be obtained. Bearing in mind the FPGA resources, we have developed LALP, a novel language to program FPGAs. A compilation framework including mapping capabilities supports the language. The main ideas behind LALP is to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to permit the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. In this paper we describe LALP, and show how it can be used to achieve high-performance computing solutions.

On using LALP to map an audio encoder/decoder on FPGAs

This paper presents the use of LALP to implement typical industrial application kernels, ADPCM Encoder and Decoder, in FPGAs. LALP is a domain specific language and its compilation framework aims to the direct mapping of algorithms originally described in a high-level language onto FPGAs. In particular, LALP focuses on loop pipelining, a key technique for the design of hardware accelerators. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware. We present experimental results showing significant performance gains using this approach, while still keeping the language syntax and semantics close to popular high level software languages, a desirable feature when considering time to market constraints. We believe the performance gains observed for the ADPCM implementation can be extended to other industrial applications relying on algorithms spending most of their execution time on loop structures, such signal and image processing.

Automatic generation of FPGA hardware accelerators using a domain specific language

This paper describes an alternative approach to direct mapping loops described in high-level languages onto FPGAs. Different from other approaches, this technique does not inherit from software pipelining techniques. The control is distributed over operations, thus a finite state machine is not necessary to control the order of operations, allowing efficient hardware implementations. The specification of a hardware block is done by means of LALP, a domain specific language specially designed to help the application of the techniques. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware blocks.

Teaching embedded systems with FPGAs throughout a computer science course

Although embedded systems have been around for quite a long time, just in recent years they have attracted major industry and academic interest. There is a perception that a computing paradigm shift is taking place, and so the need to provide computer science students with the required expertise in the field. In this paper we describe our experience of using a reconfigurable computing platform throughout a number of courses. By doing so we allow students to get acquired to embedded systems concepts and practices under different contexts in the normal curriculum. The application of this strategy have allowed considerable gains for students taking embedded system courses, research projects in the field, and also professional activities.

Towards the Characterization of Monitor Smells in Adaptive Systems

Adaptive Systems (ASs) can adapt themselves to achanging environment or new user needs. Monitors are essential in AS, being responsible for collecting and processing data from environment. There exist different kinds of monitors with distinct characteristics. Based on a literature review, we have noticed that Monitors are usually designed and implemented in an inadequate way: i) making them obscure in the source-code, ii) compelling all of them to have the same polling rate and also iii) predetermining the execution order among them. This leads to maintenance, evolution and performance problems. Besides, based on our observations, this erroneous way monitors are implemented follows a pattern and it is a recurrent practice. Therefore, we believe it can be classified as Monitor Smells of Adaptive Systems. In this paper we present two architectural smells we have identified: the Obscure Monitor and the Oppressed Monitors. The first smell occurs when the monitors are not evident in the source-code. The second smell occurs when monitors are compelled to have the same poling rate and an immutable execution order at runtime. The presence of these smells compromises the reusability, evolvability and maintainability. We have also conducted an exploratory study by comparing the impact of maintenance tasks in the original version of an AS called PhoneAdapter with a refactored version, in which the smells were removed. The results indicate the maintenance is facilitated in the version without the smells.

Experimenting with a Multi-Approach Testing Strategy for Adaptive Systems

Context: Testing adaptive systems (ASs) is particularly challenging due to certain characteristics such as the high number of possible configurations, runtime adaptations and the interactions between the system and its surrounding environment. Therefore, the combination of different testing approaches in order to compose a strategy is expected to improve the quality of the designed test suites. Objective: To devise and experiment with a testing strategy for ASs that relies on particular characteristics of these systems. Method: We ranked testing approaches for ASs and devised a strategy that is composed of the three top-ranked ones. The rankings address the challenges that can be mitigated by the approaches, activities from a typical testing process, and characteristics observed in some AS implementations. The strategy was applied to two adaptive systems for mobile devices. Results: The approach was applied to both systems. We observed partial gains in terms of fault detection and structural coverage when results are analysed separately for each system, even though no improvements were obtained with the application of the third approach. Conclusion: The strategy, despite being incipient, is promising and motivates a deeper analysis of results and new experiment rounds. Furthermore, it can evolve as long as the rankings are updated with new approaches.