Marco Aurelio Nuño-Maganda

Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling

One of the most extended algorithms for image scaling is bicubic interpolation. In this paper, a hardware architecture for bicubic interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the interpolation coefficients, which implements the bicubic function to be used in HABI; the second one performs the interpolation process and the third one is a control unit that synchronizes the processing and the pipeline stages. The architecture work with monochromatic images, but it can be extended for working with RGB color images. Our design description is coded in Handel-C language and implemented on a Xilinx Virtex II Pro FPGA. The proposed system runs 10 times faster than an Intel Pentium 4-based PC at 2.4 GHz. Comparison with other related works are provided

Robust smartphone-based human activity recognition using a tri-axial accelerometer

Mobile artifacts such as smartphones have made possible the development of wearable systems for user activity monitoring and recognition due to the synergy of communication, computation and sensing capabilities in battery-powered systems-on-chip. Due to user acceptability, smartphones are able to measure nonintrusively proprioceptive motion outside of a controlled environment for rather long periods of time using embedded inertial sensors. Though work has been done for accelerometer-based activity recognition, the portability of the smartphone to a single fixed tight position has been a major constraint to easy the interpretation of the collected data. In this paper, a human activity hierarchical recognition system based on time-domain features and neural networks without the need of the smartphone to be constrained to a single fixed body position is presented. Experimental results on Android-capable smartphones on four on-body locations show that the recognition system achieves high classification rates, above 92%, for five activities including static, walking, running, and up-down stairs walking, running continuously in near real-time with reduced power consumption.

Comparison between 2D cellular automata based pseudorandom number generators

Pseudorandom number generators (PRNGs) should satisfy two main criteria, high randomness quality and fast computation of a sequence of numbers. In this paper, a comparative study of twodimensional Cellular Automata (CA) based PRNGs is performed to evaluate the randomness quality and the hardware constraints involved in terms of configuration parameters such as, transition rules, neighborhoods and bit extraction schemes. Experimental results show that CA-based PRNGs present good randomness quality using standard test suites, and they are well suited for parallel implementations in Field Programmable Gate Array (FPGA) technology taking advantage of the on-chip fine-grain and distributed computational resources.

Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms

Spiking Neural Networks (SNNs) have become an important research theme due to new discoveries and advances in neurophysiology, which states that information among neurons is interchanged via pulses or spikes. FPGAs are widely used for implementing high performance digital hardware systems, due to its flexibility and because they are suitable for the implementation of systems with high degree of parallelism. FPGAs have become an important tool because fine grain digital elements useful for efficient hardware implementation of SNNs are provided, making FPGA device suitable for implementing SNNs. Several attempts for implementing efficient classifiers in hardware have been done, but most of them fail because the processing elements are costly in terms of hardware resource utilization. SNNs are less hardware greedy, and the nature of the pulsed processing is well suited to the digital processing blocks of the FPGA devices. In this work, a hardware architecture for implementing both recall and learning phases required for Multilayer FeedForward SNNs is proposed. Results and performance statics are provided.

A temporal coding hardware implementation for spiking neural networks

Spiking Neural Networks (SNNs) models have been explored in recent years due to its biological plausibility where temporal coding plays an important role. Biological arguments and computational experiments suggest than some perceptual tasks (vision and olfaction for instance) are well performed by these models. Moreover, some other applications such as machine learning might be benefited from this approach. However, efficient simulation and implementation of SNNs still remain an open challenge. There are several issues that must be addressed, being one of them the temporal coding of real-value data itself. In order to study the possibilities of embedded real-time implementations of large scale SNNs, we have first chosen to implement a well-known coding scheme based on Gaussian Receptive Fields (GRFs) to map real-value data into spike trains. This paper proposes a configurable parallel FPGA based accelerator for GRF-based temporal coding. The proposed architecture of the hardware implementation is described in detail and implementation results, both performance and resource utilization, when mapped to a Virtex-II Pro FPGA device are reported.

Elliptic curve cryptography on Windows CE devices

Since mobile devices were conceived and commercialized, their market has grown exponentially, so as its problems related to secure data residing in them. Elliptic curve cryptography (ECC) is an approach to public key cryptography (PCK) based on the algebraic structure of elliptic curves over finite fields. It represents the most suitable choice for implementing cryptography in mobile devices since it uses smaller key sizes compared with others traditional public key cryptosystems without decreasing the security level. In this work we present the design of software modules for ECC over .Net Compact Framework (.Net CF) 3.5 well suited for mobile and embedded devices with Windows CE as operating system. The main cores are modules for finite field arithmetic and elliptic curve cryptographic schemes defined over the prime field Zp. These modules are not available neither in the programming language nor the .Net CF. We evaluated the performance of our implementations using the Personal Digital Assistant devices IPAQ 116 and Handheld HP 216, using elliptic curves over the prime field Zp with p=192, 224 and 256, which are key sizes currently recommended by NIST. Our results show that ECC could be implemented in .Net CF with a performance that should be tolerated by most of the users with a high degree of security.

A novel strategy for image segmentation of latent fingerprints

Digital image segmentation is one of the most important stages in the implementation of an Automatic Fingerprint Identification System. This work describes a strategy for image segmentation of latent fingerprints using a proper combination of operators achieving better results than other approaches reported in the literature. Latent fingerprint images are low quality images that make more difficult the segmentation process. The proposed segmentation strategy is based on the gradient magnitude of the image and the detection of regions. This strategy was implemented in Matlab and Java, and was tested using fingerprint images of the Fingerprint Verification Competition databases, which are commonly used for these purposes. The results achieved show a significant improvement compared with representative algorithms of literature, such as those based on the variance of image.

Evaluation of machine learning techniques for face detection and recognition

Biometric identification (BI) is one of the most explored topics in recent years. One of the most important techniques for BI is face recognition. Face recognition systems (FRSs) are an important field in computer vision, because it represents a non-invasive BI technique. In this paper, a FRS is proposed. In the first step, a face detection algorithm is used for extracting faces from video frames (training videos) and generating a face database. In a second step, filtering and preprocessing are applied to face images obtained in the previous step. In a third step, a collection of machine learning algorithms are trained using as input data the faces obtained in the previous step. Finally, the classifiers are used for classify faces obtained from video frames (test videos). The obtained results shows the suitability of this approach for analyzing large collections of videos where previous face labels are not available.

A Hardware Coprocessor Integrated with OpenCV for Edge Detection Using Cellular Neural Networks

In this work, a high performance hardware coprocessor for CNNs and its interaction with the OpenCV library is reported. Edge detection algorithms reduce the amount of image data to be processed, because only essential information is preserved. There are several approaches for edge detection, one of them is based on Cellular Neural Networks (CNNs). The parallel nature of CNNs makes them suitable to be implemented on a reconfigurable device, such as Field Programmable Gate Arrays (FPGAs). An FPGA implementation of CNNs achieves high performance and flexibility due to fine-grain parallelism of the FPGA-based implementations. CNNs can perform both linear and nonlinear image processing tasks, such as filtering, threshold, various mathematical morphology operations, edge detection, corner detection, etc., but in this paper only the edge detection problem is addressed. Hardware resources and performance comparison are reported.

Embedded Image Processing System for Automatic Page Segmentation of Open Book Images

In this paper the image processing stage of an automatic book scanning system is presented. The scanning system is composed of a camera, an image processing platform, an illumination subsystem and a hardware platform which holds an open book to an adequate distance to the camera. The image processing platform communicates to a camera in order to obtain the input image of open book. Once the open book image acquired, the image processing stage applies a set of operators over the image in order to segment and store images of the individual book pages. Segmentation analysis and performance evaluation of the proposed image processing platform are performed. Results of the segmentation process show that at least 75% of the pages are correctly segmented. Execution time results show that up to 18 pages per minute can be automatically digitalized. The proposed system was implemented on two different processing platforms, a laptop computer with an Intel processor and a Raspberry-Pi minicomputer.