Miguel O. Arias-Estrada

Real-time image processing with a compact FPGA-based systolic architecture

Abstract In this paper, a configurable systolic architecture on a chip for real-time window-based image processing is presented. The architecture was specially designed to implement efficiently, both in performance and hardware resource utilization, window-based image operators under real-time constraints. The computational core of the architecture is a configurable 2D systolic array of processing elements, which can provide throughputs over tenths of Giga Operations per Second (GOPs). The architecture employs a novel-addressing scheme that significantly reduces the memory access overhead and makes explicit the data parallelism at a low temporal storage cost. A specialized processing element, called Configurable Window Processor (CWP), was designed to cover a broad range of window-based image algorithms. The functionality of the CWPs can be modified through configuration registers according to a given application. For a current Field Programmable Gate Array (FPGA) prototype of a 7×7 systolic array, the architecture provides a throughput of 3.16xa0GOPs at a 60xa0MHz clock frequency. The processing time for a 7×7 generic window-based image operator on 512×512 gray-level images is 8.35xa0ms. The implemented window-based image operators include generic image convolution, gray-level image morphology and template matching. According to theoretical and experimental results, the architecture compares favorably with other dedicated architectures in terms of performance and hardware resource utilization.

FPGA-based configurable systolic architecture for window-based image processing

Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of GOPs at a 60 MHz clock frequency and a processing time of milliseconds for generic window-based operators on gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.

An FPGA architecture for high speed edge and corner detection

This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per second). The architecture design was centred on the minimization on the number of accesses to the image memory. The design is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture design, FPGA resources utilization, results, and real time performance are discussed.

Motion vision sensor architecture with asynchronous self-signaling pixels

A custom CMOS imager with integrated motion computation is described. The architecture is based on correlating in time moving edges. Edges are located in time by a custom sensor; and correlated in a coprocessing module. The sensor architecture is centered around a compact pixel with analog signal processing and digital self-signaling capabilities. The sensor pixels detect moving edges in the image and communicate their position using an address-event protocol associated to temporal stamps. The coprocessing module correlates the edges and computes the velocity vector map. The motion sensor could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The article details the motion sensor architecture, the simulated performance, the VLSI implementation and some preliminary results on fabricated prototypes.

A Focal Plane Architecture for Motion Computation

A new focal plane architecture for motion computation is presented. The design is based on the Smart Sensor paradigm: combining transduction and early processing at sensor level. The sensor computes focal plane motion and direction in a subsampled space, with programmable spatio-temporal bandwidth. The architecture is designed around an array of neuromorphic analog processing cells with local photo-transduction, computation of temporal variations in the image and correlation between neighbor pixels. The inherent process of serial read-out is used for further integration of low-level processing and reduction of complexity of each pixel. An external dedicated digital processor controls the system, interprets, and integrates the information from sets of four processing pixels in order to create a motion-based medium-level description of the image. The approach developed for VLSI implementation offers an excellent combination of small pixel area and a computationally efficient method for image motion measurement. The architecture is being implemented in a standard 1.5 ?m CMOS process.

Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms

Spiking Neural Networks (SNNs) have become an important research theme due to new discoveries and advances in neurophysiology, which states that information among neurons is interchanged via pulses or spikes. FPGAs are widely used for implementing high performance digital hardware systems, due to its flexibility and because they are suitable for the implementation of systems with high degree of parallelism. FPGAs have become an important tool because fine grain digital elements useful for efficient hardware implementation of SNNs are provided, making FPGA device suitable for implementing SNNs. Several attempts for implementing efficient classifiers in hardware have been done, but most of them fail because the processing elements are costly in terms of hardware resource utilization. SNNs are less hardware greedy, and the nature of the pulsed processing is well suited to the digital processing blocks of the FPGA devices. In this work, a hardware architecture for implementing both recall and learning phases required for Multilayer FeedForward SNNs is proposed. Results and performance statics are provided.

FPGA based computer vision camera

A computer vision camera prototype for real-time applications has been developed. The camera integrates a CMOS image sensor, an FPGA based coprocessing card, and an embedded PC for communication and control tasks. The system is targeted to computer vision tasks where low level processing and feature extraction can be implemented in the PPGA device. The PPGA coprocessing card integrates a medium size FPGA from Xilinx (XC4025E) with two memory banks, an ISA interface, and an image sensor interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system. The camera can be used for hardware/software codesign, research on new computer vision architectures or educational purposes.

Remote hardware-reconfigurable robotic camera

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

A population coding hardware architecture for Spiking Neural Networks applications

Recently, Spiking Neural Networks (SNNs) have obtained the interest of Machine Learning researchers due to the rich dynamics shown by these information processing models. One of the most important problems that must be addressed for implementing efficient SNNs is the information encoding. In this paper, an implementation of a high-performance hardware architecture for population information coding based on Gaussian Receptive Fields (GRFs) is proposed. This architecture can be useful for data classifying and clustering applications, because this coding scheme has been used in the past, and an efficient mapping of this technique in hardware can improve the actual performance of these applications. The GRFs information coding can be efficiently implemented on FPGA technology, because it contains several operations that can be computed in parallel like the exponential function. The proposed hardware architecture was implemented, tested and validated with several random datasets. The proposed hardware core is the first step for implementing successfully classifiers like SpikeProp algorithm. Synthesis and timing results for the proposed hardware architecture are presented.

Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity

This paper presents a biologically inspired modular hardware implementation of a cortical model of orientation selectivity of the visual stimuli in the primary visual cortex targeted to a Field Programmable Gate Array (FPGA) device. The architecture mimics the functionality and organization of neurons through spatial Gabor-like filtering and the so-called cortical hypercolumnar organization. A systolic array and a suitable image addressing scheme are used to partially overcome the von Neumann bottleneck of monolithic memory organization in conventional microprocessor-based system by processing small and local amounts of sensory information (image tiles) in an incremental way. A real-time FPGA implementation is presented for 8 different orientations and aspects such as flexibility, scalability, performance and precision are discussed to show the plausibility of implementing biologically-inspired processing for early visual perception in digital devices.