Marco Bellini

The radial layout design concept for the Bi-mode insulated gate transistor

In this paper we present a new radial design concept for an optimized layout of anode shorts in the Bi-mode Insulating Gate Transistor (BiGT). The study shows that the arrangement of the n+-stripes plays a key role for the on-state characteristics of the BiGT. With the aid of 3D device simulations the visualization of the plasma distribution during the on-state conduction was obtained in a 0.25 × 4 mm2 large BiGT model area. The influence of the dimensioning and layout of the anode shorts was simulated and compared with measured on-state curves. A clear improvement of plasma distribution in the device when the stripes are arranged orthogonally (radially) to the pilot-IGBT boundary is observed in 3D simulations. Measurements confirm lower on-state losses as a result of better utilization of the device area.

Characterization of 6.5 kV IGBTs for High-Power Medium-Frequency Soft-Switched Applications

Medium voltage high-power applications are usually realized using high voltage semiconductors (3.3 kV and above) operated in the hard switching mode with low switching frequencies (several hundreds of hertz). However, for high-power dc-dc converters employing a transformer for galvanic isolation, it is attractive to increase the switching frequency so that the transformer size can be reduced. An increase of the switching frequency implies an increase of the switching losses, and this has to be mitigated somehow, usually by choice of resonant topologies or soft switching techniques. Main focus of the paper is on the operation of the insulated gate bipolar transistor (IGBT) within a high-power dc-dc LLC resonant converter, in order to explore interactions between semiconductor and circuit properties, which both must be simultaneously considered in order to achieve the best utilization of a high voltage power semiconductor operating at higher switching frequencies. For these purposes, switching properties of a standard 6.5 kV IGBT are compared with switching properties of two different optimized versions of a 6.5 kV IGBT. Experimental results are included to support theoretical considerations and findings.

The concept of Bi-mode Gate Commutated Thyristor-A new type of reverse conducting IGCT

In this paper, a new type of reverse conducting IGCT referred to as Bi-mode Gate Commutated Thyristor (BGCT) is discussed. The concept of the BGCT follows an interdigitated integration approach of an IGCT and Diode into a single structure while utilizing the same silicon volume in both GCT and Diode modes. This results in improved thermal behavior and current capability. The BGCT design concept differs from that of the conventional Reverse Conducting IGCT (RC-IGCT) since in the BGCT, each individual segment is designed either as a GCT cathode or Diode anode. With the aid of 2-D Sentaurus TCAD device simulations, we have compared the static and dynamic characteristics of a 91 mm 4.5 kV BGCT model in both GCT and diode modes with that of the equivalent RC-IGCT and asymmetric IGCT. Furthermore, we have also investigated the BGCT performance by varying the GCT to Diode segments ratio.

A novel ultra-low loss four inch thyristor for UHVDC

We introduce a new generation of 100 mm electrically triggered phase controlled thyristor (PCT) with on-state voltage VT <; 1.6 V at IT = 1.5 kA and T = 90 °C and nominal forward and reverse blocking voltages of 8.5 kV. This PCT employs a new junction termination, which allows us to reduce the original device thickness by 7 % and hereby the VT by 13 %. This device has thinner p-type active regions with both the wafer and doping profiles specially shaped around the negative bevel. As a result, the reach-through effect is absent in the active area, the leakage current is reduced and the maximal junction temperature is increased by 25 °C.

Inherently soft free-wheeling diode for high temperature operation

Traditionally, the major driver in IGBT and diode development is to minimize the static and dynamic losses. A significant reduction of the n-base thickness would yield this, however it can also jeopardize the switching characteristic leading to high overshoot voltages during diode reverse recovery. In this paper, we present an improved Field-Charge Extraction (FCE) concept that is achieving a soft reverse recovery behavior inherently. The new design allows for a 10% reduction of the thickness of the diodes n-base, while still maintaining the blocking capability and the softness of the conventional diode. Therefore, the technology curve and the ruggedness are improved significantly.

On the Performance of Multiobjective Evolutionary Algorithms in Automatic Parameter Extraction of Power Diodes

In this paper, a general, robust, and automatic parameter extraction of nonlinear compact models is presented. The parameter extraction is based on multiobjective optimization using evolutionary algorithms, which allow fitting of several highly nonlinear and highly conflicting characteristics simultaneously. Two multiobjective evolutionary algorithms which have been proved to be robust for a wide range of multiobjective problems [1]-[3], the nondominated sorting genetic algorithm II and the multiobjective covariance matrix adaptation evolution strategy, are used in the parameter extraction of a novel power diode compact model based on the lumped charge technique. The performance of the algorithms is assessed using a systematic statistical approach. Good agreement between the simulated and measured characteristics of the power diode shows the accuracy of the used compact model and the efficiency and effectiveness of the proposed multiobjective optimization scheme.

Robust 3.3kV silicon carbide MOSFETs with surge and short circuit capability

An approach to implement electrically robust MOSFETs in a functioning half-bridge will be investigated. For the first time, reverse conducting 3.3kV SiC MOSFETs have been fabricated with dilferent cell pitches from 14μm (p1.0) to 26μm (pl.8) that are able to withstand short circuit pulse of up to 10μs and a 9ms surge current event up to 15x the nominal current. LinPak half-bridge modules have been fabricated showing reduction of the switching loss by more than 90% compared to a silicon IGBT/diode half bridge.

Large-scale 3D TCAD study of the impact of shorts in phase controlled thyristors

Continuous advances in computer hardware and solving algorithm enable more pervasive use of 3D TCAD simulations for both nanoscale and power semiconductor devices. However, while BiMOS power semiconductor devices such as IGBTs require relatively small 3D simulated structures (of the order of fa 10×10×1000/im3), bipolar power devices such as thyristors require much larger simulated structures of the order of fa 10 mm3. This work presents large scale 3D simulations of Phase Controlled Thyristors and describes the technique used to reduce computation times to extents compatible with industrial practice. 3D TCAD is used to understand the impact of cathode shorts on figures of merit such as the breakdown voltage and dV/dt.

3D TCAD analysis of the effect on dI/dt of cathode shorts in Phase Controlled Thyristors

This work presents a comprehensive overview of role played by cathode shorts in Phase Controlled Thyristors (PCTs), combining large scale 3D TCAD simulations and experimental data. The impact of shorts on breakdown voltage (BV), dV/dt and on-state voltage (VT) is reviewed, discussing tradeoffs and optimization in device design based on the placement of the shorts. Moreover, the present work utilizes large scale 3D simulations of Phase Controlled Thyristors to shed more light on the impact of shorting patterns on the dI/dt of PCTs. The use of complex meshes with a realistic short pattern and ad-hoc post-processing techniques offer additional insight on phenomena that have been treated mainly with simplified analytical models [1][2][3] or approximate numerical methods [4], allowing for improved device design.

Programmable mask design for Phase Controlled Thyristors with automated short positioning

Procedural layout generation is common practice in digital, analog or RF circuit layout design. Designers generate mask designs by specifying only the key parameters of devices, digital or analog blocks and have algorithms construct the complete layout. But automated layout design is limited to Manhattan structures (orthogonal shapes) or to devices with 45° angles (typically octagonal inductors). This work introduces for the first time procedural layout generation to wafer-size power semiconductor devices such as Phase Controlled Thyristors (PCTs), characterized by arbitrary angles and shapes, including curved geometries. The proposed technique offers many advantages such as saving of time, automatic enforcement of design rules and best practices, and ease of modification of an existing design. In particular, this work focuses mainly on the key advantage of this approach: device performance and reliability improvement through automated placement of the PCT shorts.