R. A. Minamisawa

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

Strained Si nanowires are among the most promising transistor structures for implementation in very large-scale integration due to of their superior electrostatic control and enhanced transport properties. Realizing even higher strain levels within such nanowires are thus one of the current challenges in microelectronics. Here we achieve 4.5% of elastic strain (7.6 GPa uniaxial tensile stress) in 30 nm wide Si nanowires, which considerably exceeds the limit that can be obtained using SiGe-based virtual substrates. Our approach is based on strain accumulation mechanisms in suspended dumbbell-shaped bridges patterned on strained Si-on-insulator, and is compatible with complementary metal oxide semiconductor fabrication. Potentially, this method can be applied to any tensile prestrained layer, provided the layer can be released from the substrate, enabling the fabrication of a variety of strained semiconductors with unique properties for applications in nanoelectronics, photonics and photovoltaics. This method also opens up opportunities for research on strained materials.

Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs

In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with p-doped compressively strained Si0.5Ge0.5 source, intrinsic Si channel, and n-doped Si drain. We observe a linear relation of gate length, Lg, and ON-current, ION, which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation.

Power-dependent Raman analysis of highly strained Si nanobridges.

Strain analysis of complex three-dimensional nanobridges conducted via Raman spectroscopy requires careful experimentation and data analysis supported by simulations. A method combining micro-Raman spectroscopy with finite element analysis is presented, enabling a detailed understanding of strain-sensitive Raman data measured on Si nanobridges. Power-dependent measurements are required to account for the a priori unknown scattering efficiency related to size and geometry. The experimental data is used to assess the validity of previously published phonon deformation potentials.

Characterization of a Silicon IGBT and Silicon Carbide MOSFET Cross-Switch Hybrid

A parallel arrangement of a silicon (Si) IGBT and a silicon carbide (SiC) MOSFET is experimentally demonstrated. The concept referred to as the cross-switch (XS) hybrid aims to reach optimum power device performance by providing low static and dynamic losses while improving the overall electrical and thermal properties due to the combination of both the bipolar Si IGBT and unipolar SiC MOSFET characteristics. For the purpose of demonstrating the XS hybrid, the parallel configuration is implemented experimentally in a single package for devices rated at 1200 V. Test results are obtained to validate this approach with respect to the static and dynamic performance when compared to a full Si IGBT and a full SiC MOSFET reference devices having the same power ratings as for the XS hybrid samples.

Unipolar behavior of asymmetrically doped strained Si0.5Ge0.5 tunneling field-effect transistors

We investigate here the impact of the dopant concentration in the source and drain regions on the ambipolar behavior of band-to-band tunneling field-effect transistors with compressively strained Si0.5Ge0.5 channels grown on Si on insulator. Source and drain areas were formed by BF2+ and As+ ion implantation to doses of 1 × 1013, 1 × 1014, and 1 × 1015 cm−2. We show that the dopant concentration impacts the energy band alignment of source/drain and the channel region, and thus influences the tunneling current. The ambipolar device behavior is strongly reduced toward unipolar for source-to-drain implantation dose ratio of 100, but at the expense of the on-current, as compared to symmetric implanted devices. Moreover, our results indicate that for SiGe devices, the change of the B doping concentration has a greater impact on the tunneling currents than the variation of the As concentration.

A Patterning-Based Strain Engineering for Sub-22 nm Node FinFETs

We propose a strain engineering approach that is based on the patterning and under etching of fins using strained Si grown on SiGe strain relaxed buffers. The method enhances the strain of the patterned Fins up to ~ 2.9 GPa without the need of epitaxial source and drain stressors. We report a systematic simulation study on the scaling of this method for the present and future technology nodes down to 7 nm. Finally, we estimate that the technique deliveries an electron mobility enhancement up to 87% for FinFETs, independent of the technology node.

Robust 3.3kV silicon carbide MOSFETs with surge and short circuit capability

An approach to implement electrically robust MOSFETs in a functioning half-bridge will be investigated. For the first time, reverse conducting 3.3kV SiC MOSFETs have been fabricated with dilferent cell pitches from 14μm (p1.0) to 26μm (pl.8) that are able to withstand short circuit pulse of up to 10μs and a 9ms surge current event up to 15x the nominal current. LinPak half-bridge modules have been fabricated showing reduction of the switching loss by more than 90% compared to a silicon IGBT/diode half bridge.

Ultra-Thin Epitaxial Tungsten Carbide Schottky Contacts in 4H-SiC

We demonstrate the fabrication and characterization of epitaxial W2C Schottky contacts into 4H-SiC via sputtering deposition of ultra-thin W followed by thermal annealing. The alloying reaction occurs below 600 °C, yielding a stable layer up to 1200 °C. The epitaxial layer is hexagonal, unexpectedly forming W2C phase even at the lowest annealing temperature, which is predicted to occur at 1500 °C in bulk systems. Schottky contacts based on epitaxial W2C films exhibit smoother interface morphology, higher thermal stability, lower turn-ON voltage and about ~50% reduction in Schottky-contact resistance compared with thick Ti Schottky contacts.

Current Sharing Behavior in Si IGBT and SiC MOSFET Cross-Switch Hybrid

The cross hybrid (XS) concept has been demonstrated experimentally with 3.3-kV Si Insulated Gate Bipolar Transistor (IGBTs) and SiC MOSFETs in parallel, and used to calibrate 2D Technology Computer Aided Design simulations. The XS hybrid offers lower switching losses compared with full Si IGBTs and reduced oscillations compared with full SiC MOSFETs. The current sharing mechanism between the IGBT and the MOSFET in the XS hybrid has been elucidated, showing that under typical switching conditions, the IGBT dissipate 98% of the XS hybrid turn-OFF losses compared with the SiC MOSFET. Since the current density of the IGBT in the XS hybrid is twice of that of the full IGBT solution, it exhibits higher dynamic avalanche. These features results in stress at device and package level, thereby compromising robustness and reliability. In order to overcome such issues, we show that increasing the turn-OFF gate resistance improves current sharing in the XS hybrid by delaying the turn-OFF of the MOSFET, and thereby suppressing dynamic avalanche in the IGBT.

Simulation and experimental results of 3.3kV cross switch “Si-IGBT and SiC-MOSFET” hybrid

In this work we present the simulation and experimental results of the “Cross Switch (XS)-Hybrid” built with 3.3kV Si-IGBTs and SiC-MOSFETs. We have analyzed the switching performance, mainly the turn-off behavior of the XS-Hybrid (a parallel arrangement of a Si-IGBT and a SiC-MOSFET) with the aid of Sentaurus TCAD device simulations. We discuss in detail the current sharing mechanism between these two devices and hence the distribution of the turn-off losses and the stress (peak power density, dynamic avalanche) on the devices during switching. In addition, we have investigated the turn-off behavior of the XS-Hybrid by variation of the area ratio between the Si-IGBT and SiC-MOSFET, variation of the gate resistance, and variation of the gate resistance ratio. To investigate the switching behavior of the XS-Hybrid, first the simulation models have been adjusted to match the experimental results of the 3.3kV Si-IGBT and SiC-MOSFET. Furthermore, the simulation and experimental results of the 3.3kV XS-Hybrid are compared with the full 3.3kV Si-IGBT and full 3.3kV SiC-MOSFET reference devices.