Thomas Jean Ludovic Baglin

A very low drop voltage regulator using an NMOS output transistor

A very low drop voltage regulator that uses an NMOS output transistor, a start-up circuit and two voltage comparators, designed in a 0.12 /spl mu/m CMOS technology, is presented. By means of a charge pump to control the gate of the NMOS transistor it is possible to obtain the very low voltage drop, between input and output, of only 100 mV. A novel sample and hold technique is used in order to slow down the charge pump and to save current in low power mode. The start-up circuit comprises a simple PMOS regulator and works without the accurate reference voltage of a bandgap, which is not stable during the first few microseconds. The regulator works in a wide load area from 20 /spl mu/A - its own current consumption - up to 50 mA, does not require any additional capacitors at its outputs and provides a low power mode.