Marco Ferraro

4-Mb MOSFET-selected phase-change memory experimental chip

This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-/spl mu/m CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

4-Mb MOSFET-selected /spl mu/trench phase-change memory experimental chip

A /spl mu/trench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18-/spl mu/m CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.