Maria J. Avedillo

VLSI implementations of threshold logic-a comprehensive survey

This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

A practical floating-gate Muller-C element using vMOS threshold gates

This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation.

A threshold logic synthesis tool for RTD circuits

Functional devices and circuits based on resonant tunneling diodes (RTD) are receiving much attention since they allow high speed and/or low power operation. RTDs exhibit a negative differential resistance in their current-voltage characteristic which can be exploited to significantly increase the functionality implemented by a single gate in comparison to other technologies. In particular, they have proven to efficiently implement threshold gates which are a generalization of conventional Boolean gates. Suitable logic synthesis tools are required to handle these complex building blocks in order to translate the advantages of this emergent technology to the circuit and system levels. This paper describes an efficient approach to the automatic design of networks of threshold gates from functional specifications. Results for widely used logic functions and standard benchmark circuits are reported.

Using multi-threshold threshold gates in RTD-based logic design: A case study

The basic building blocks for resonant tunneling diode (RTD) logic circuits are threshold gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, TGs can be implemented as efficiently as conventional ones, but realize more complex functions. Recently, RTD structures implementing multi-threshold threshold gates (MTTGs) have been proposed which further increase the functionality of the original TGs while maintaining their operating principle and allowing also the implementation of nanopipelining at the gate level. This paper describes the design of n-bit adders using these MTTGs. A comparison with a design based on TGs is carried out showing advantages in terms of power consumption and power delay product.

Increased Logic Functionality of Clocked Series-Connected RTDS

The augmentation of transistor technologies with resonant tunnelling diodes (RTDs) has demonstrated improved circuit performance. The negative differential resistance exhibited by these devices can be exploited to increase the functionality implemented by a single gate in comparison to transistor-only technologies. Complex threshold gates (TGs) are efficiently realized by resorting to the operation principle of the clocked series connection of a pair of RTDs (MOBILE). This paper focuses the implementation of logic blocks using RTDs and transistors which further increase the functionality of previously reported topologies. Multithreshold-threshold gates (MTTGs) is the logic concept underlying the proposed realizations. The MOBILE principle is extended to three or more RTDs in series which allows us to implement MTTGs. Novel and extremely compact realizations of programmable gates using the MTTG topology are presented. A number of logic blocks useful for digital design are shown and their operation is verified through simulation with extensively validated models for actual devices

Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors

One of the most attractive features of MOBILE-based circuits is their self-latching operation, which allows pipelining at the gate level, and thus very high through-output, without any area overhead associated to the addition of the latches. However, the self-latching behavior is not inherent to the practical circuit topologies employed to implement MOBILE circuits. This paper reports on very simple MOBILE structures supporting this statement. The analysis performed is useful in extracting design guidelines to guarantee the required behavior.

Logic models supporting the design of MOBILE-based RTD circuits

Threshold logic is a computational model widely used in the design of resonant tunnelling diodes (RTDs) based circuits, i.e. these circuits are built from threshold gates. This paper explores two other computational models, generalized threshold gates (GTG) and multi-threshold threshold gates (MTTGs), also suitable to be realized with mobile based RTD structures. Circuits implementing them are described. Both logic models are generalizations of threshold logic and so the proposed circuit topologies further increase the functionality of the original TGs. Implementations of a non threshold function with the GTG and MTTG topologies are shown and compared.

Analysis of frequency divider RTD circuits

The behavior of a novel circuit topology able to implement a frequency divider is studied. This circuit is composed of a resonant tunnelling diode (RTD), an inductor, and a capacitor, so it exhibits a very high operating frequency and low power consumption. It employs the period-adding sequences which appear in its bifurcation diagram to perform the frequency division. Compared to a previously reported similar circuit, it has wider operation windows and a higher division factor for the driver frequency, while maintaining the extremely high operating frequency, its simplicity, and the division factor tunability through the selection of circuit parameters. Simulation results using the HSPICE RTD model from project LOCOM as well as several realistic parasitics elements are given, which confirm the theoretical capabilities previously analyzed.

Improved Nanopipelined RTD Adder Using Generalized Threshold Gates

Many logic circuit applications of resonant tunneling diodes are based on the monostable-bistable logic element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e., these circuits are built from threshold gates (TGs). This paper describes the design of full adders (FAs), using TG-based circuit topologies. Both the selection of different MOBILE TG networks and the use of gates that can be considered extensions of the MOBILE TG are addressed. The FAs are applied to the design of nanopipelined carry propagations adders, which are evaluated and compared to a previously reported one, showing advantages in terms of speed, power, and power-delay product.

SMAS: a program for the concurrent state reduction and state assignment of finite state machines

A state assignment algorithm for PLA-based machines which produces as assignment of nonnecessarily distinct and eventually incompletely specified codes is presented. In this approach, state reduction and state assignment are concurrently dealt with, and a restricted state splitting technique is explored. The algorithm is particularly appropriate for machines with compatibility relations among states because the potentials of state merging are exploited during the state assignment step. The input to SMAS, the program implementing the algorithm, is a symbolic cover of the FSM. The output is a Boolean representation of both next state and output functions suitable to be minimized with ESPRESSO. The machines in the MCNC benchmark set are used to test the algorithm and to compare it with a well-known state assignment program.<<ETX>>