Mariangela Genovese

ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition Video

Background identification is a common feature in many video processing systems. This paper proposes two hardware implementations of the OpenCV version of the Gaussian mixture model (GMM), a background identification algorithm. The implemented version of the algorithm allows a fast initialization of the background model while an innovative, hardware-oriented, formulation of the GMM equations makes the proposed circuits able to perform real-time background identification on high definition (HD) video sequences with frame size 1920 × 1080. The first of the two circuits is designed with commercial field-programmable gate-array (FPGA) devices as target. When implemented on Virtex6 vlx75t, the proposed circuit process 91 HD fps (frames per second) and uses 3% of FPGA logic resources. The second circuit is oriented to the implementation in UMC-90 nm CMOS standard cell technology, and is proposed in two versions. Both versions can process at a frame rate higher than 60 HD fps. The first version uses the constant voltage scaling technique to provide a low power implementation. It provides silicon area occupation of 28847 μm2 and energy dissipation per pixel of 15.3 pJ/pixel. The second version is designed to reduce silicon area utilization and occupies 21847 μm2 with an energy dissipation of 49.4 pJ/pixel.

Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition

The processing capabilities that are included into the acquisition block of the real-time digital oscilloscopes largely contribute to determine the overall performance of the instrument. Their remarkable improvement has made it possible to enhance the performance in terms of increased measurement rate, automation, and reduced measurement uncertainty related to quantization and noise. This paper presents the implementation of a preprocessing circuit for a novel acquisition mode of bandpass signals, which is characterized by an increased vertical resolution. Although the theoretical foundations were recently presented with simulative results, here, the circuital implementation of such an acquisition mode is presented. The focus is on mid or low cost digital oscilloscopes that can improve their vertical resolution at a negligible additional cost. First, a preliminary field programmable gate array implementation is considered to evaluate the achievable performance both from a theoretical point of view and throughout experimental tests. Then, a custom application specific integrated circuit implementation, in 28-nm complementary metal-oxide-semiconductor technology is analyzed. Along with the parameter optimization, the work experimentally tests the acquisition mode and evaluates the effects of nonideal characteristics such as finite word length and nonideal filtering. The increase in the effective number of bit (ENoB) is up to 2.5 bit, whereas the ENoB degradation because of word length and nonideal filtering is quantified as ~ 1.1 and 0.5 bit. The design highlights that there is substantial margin for parallel implementation that is the base to candidate the proposed solution as a remarkable option for the next generation oscilloscopes.

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems. The recent literature proposes various DDFS implementation techniques that, implemented by using state of the art Application Specific Integrated Circuits (ASIC) technologies, provide ever improving performances in terms of speed, power dissipation and silicon area occupation. The performance trend provided by the advanced designs that target ASIC technologies is not guaranteed to remain the same when the target technology is a commercially available Field Programmable Gate Array (FPGA) device. This paper presents the FPGA implementation of the best performing DDFS architectures proposed to date. DDFS performance trends are compared with the ASIC implementations. Further, the state of the art DDFS circuits are modified in order to better suit the FPGA technology and compared against the DDFS implementations obtained using Intellectual Properties (IPs) included in the design suites of the FPGA manufacturers. The comparison is conducted considering as implementation target various (both low end, middle range, and high end) FPGA devices produced by different vendors. Considered performance parameters are the maximum working frequency, the dynamic power dissipation, the logic resource occupation, and the precision of the DDFS measured in terms of Spurious Free Dynamic Range (SFDR). The analysis shows that when dealing with FPGA implementations, it is important that the implemented architectures adapt to the internal logic resources of the FPGA. For low SFDR values the best performing architectures are the straightforward ROM based ones that optimally fit in the very fast Block RAM of the FPGA. When the required SFDR increases more advanced architectures are required. The optimal architectures also depend on the design choice of privileging high working frequency or reduced power dissipation.

Accurate Fixed-Point Logarithmic Converter

The hardware computation of the logarithm function is required in several applications, ranging from signal and image processing to telecommunication systems. This brief shows that most of previous proposed logarithmic converters, based on piecewise linear approximations, suffer from large errors when dealing with fixed-point input values with many fractional bits, a situation often encountered in practical applications. Thus, this brief proposes a novel logarithmic converter, using nonuniform segmentation and piecewise linear approximation. A rigorous technique that allows computing the optimal segmentation and the coefficients values for a prescribed precision is described in this brief. For fixed-point input values, the proposed approach allows obtaining a sensibly lower error, for the same number of nonuniform segments, compared with previously published results. Implementation details and synthesis results in a 65-nm CMOS technology are also presented.

FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video

Circuits and systems able to process high quality video in real time are fundamental in nowadays imaging systems. The circuit proposed in the paper, aimed at the robust identification of the background in video streams, implements the improved formulation of the Gaussian Mixture Model (GMM) algorithm that is included in the OpenCV library. An innovative, hardware oriented, formulation of the GMM equations, the use of truncated binary multipliers, and ROM compression techniques allow reduced hardware complexity and increased processing capability. The proposed circuit has been designed having commercial FPGA devices as target and provides speed and logic resources occupation that overcome previously proposed implementations. The circuit, when implemented on Virtex6 or StratixIV, processes more than 45 frame per second in 1080p format and uses few percent of FPGA logic resources.

An FPGA-based Real-time Background Identification Circuit for 1080p Video

The paper proposes an improved hardware implementation of the OpenCV version of the Gaussian Mixture Model (GMM) algorithm. Truncated binary multipliers and a ROM compression technique are employed to reduce hardware complexity while increasing circuit processing capability. The OpenCV GMM algorithm is adapted to allow the FPGA implementation while providing a minimal impact on the quality of the processed videos. When implemented on Virtex5 FPGA the proposed circuit is able to process High Definition (HD) video sequences at 30 frame per second (fps) improving the performances with respect to previously proposed implementations (-7.6% in area and +12.6% in speed).

Hardware performance versus video quality trade-off for Gaussian mixture model based background identification systems

Background identification is a fundamental task in many video processing systems. The Gaussian Mixture Model is a background identification algorithm that models the pixel luminance with a mixture of K Gaussian distributions. The number of Gaussian distributions determines the accuracy of the background model and the computational complexity of the algorithm. This paper compares two hardware implementations of the Gaussian Mixture Model that use three and five Gaussians per pixel. A trade off analysis is carried out by evaluating the quality of the processed video sequences and the hardware performances. The circuits are implemented on FPGA by exploiting state of the art, hardware oriented, formulation of the Gaussian Mixture Model equations and by using truncated binary multipliers. The results suggest that the circuit that uses three Gaussian distributions provides video with good accuracy while requiring significant less resources than the option that uses five Gaussian distributions per pixel.

State of the art direct digital frequency synthesis methodologies and their performance on FPGA

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed but they optimize the performance for a given ASIC (Application Specific Integrated Circuits) technology. Nowadays, FPGA are very often used for the release of electronic systems. As a consequence, the study of the performance of advanced DDFS design techniques when implemented on FPGA devices, is of great interest. The paper presents various implementation of state of the art DDFS on various FPGA and compares their performance providing hints on optimal design as a function of the chosen performance parameter.

Processor core for real time background identification of HD video based on OpenCV Gaussian mixture model algorithm

The identification of moving objects is a fundamental step in computer vision processing chains. The development of low cost and lightweight smart cameras steadily increases the request of efficient and high performance circuits able to process high definition video in real time. The paper proposes two processor cores aimed to perform the real time background identification on High Definition (HD, 1920 1080 pixel) video streams. The implemented algorithm is the OpenCV version of the Gaussian Mixture Model (GMM), an high performance probabilistic algorithm for the segmentation of the background that is however computationally intensive and impossible to implement on general purpose CPU with the constraint of real time processing. In the proposed paper, the equations of the OpenCV GMM algorithm are optimized in such a way that a lightweight and low power implementation of the algorithm is obtained. The reported performances are also the result of the use of state of the art truncated binary multipliers and ROM compression techniques for the implementation of the non-linear functions. The first circuit has commercial FPGA devices as a target and provides speed and logic resource occupation that overcome previously proposed implementations. The second circuit is oriented to an ASIC (UMC-90nm) standard cell implementation. Both implementations are able to process more than 60 frames per second in 1080p format, a frame rate compatible with HD television.