Marijn Verbeke

Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits

In bang-bang (BB) clock and data recovery circuits (CDR) limit cycles can occur, but these limit cycles are undesired for a good operation of the BB-CDR. Surprisingly, however, a little bit of noise in the system is beneficial, because it will quench the limit cycles. Until now, authors have always assumed that there is enough noise in a BB-CDR such that no limit cycle occurs. In this work, a pseudo-linear analysis based on describing functions is used to investigate this. In particular, the relationship between the input noise and the amplitude of eventual limit cycles is investigated. An important result of the theory is that it allows to quantify the influence of the different loop parameters on the minimal amount of input jitter needed to destroy the limit cycle. Additionally, for the case that there is not enough noise, the worst case amplitude of the limit cycle (which is unavoidable in this case) is quantified as well. The presented analysis exhibits excellent matching with time domain simulations and leads to very simple analytical expressions.

CBI: a scalable energy-efficient protocol for metro/access networks

This paper presents a scalable energy-efficient MAC/PHY protocol for building a metro/access network. The proposed cascaded bit-interleaving (CBI) protocol extends the previously reported bit-interleaving concept to a multi-level paradigm. Moreover, a 40Gb/s 3-level electrical duobinary based physical layer scheme has been proposed for cost and energy saving, especially for end terminals. We compared two implementation approaches in terms of optical budget and transmission penalties. The initial estimate from the proof-ofconcept full-custom ASIC design shows that an ultra-low power metro/access network can be realized.

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Recently, there has been a strong drive to replace established analog circuits for multi-gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase locked loop-based all-digital CDR (AD-CDR) techniques which contain a digital loop filter (DLF) and a digital controlled oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050 mm2 and consumes only 46 mW at 25 Gb/s. This is the smallest area and the lowest power consumption compared with the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic, and supports a wide operating range (12.5–25 Gb/s), which is a significantly larger range compared with the previous work. Finally, thanks to our digital architecture, the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with the most prior work, making our design truly adaptive.

An 8-phase 10GHz voltage controlled ring oscillator for 40 Gbit/s BiPON clock-and-data recovery

New technologies such as cloud services and the Internet of Things have led to a demand for higher bandwidths, as well as the need for dynamic bandwidth allocation. This flexible bandwidth is offered by the BiPON protocol. By using BiPON, a significant power consumption reduction can be realized at the receiver side by using a 1:4 sub-sampling clock-and-data recovery circuit (CDR). To realize this CDR, the phase detector needs 8 phases of a 10GHz sampling clock. In this paper, we present the design and measurements of such a VCO, which has a tuning range of 6.57 GHz to 10.61 GHz and a gain of 250 MHz/V, while consuming about 30mW.

Voltage Controlled Oscillators for 40Gbit/s Cascaded Bit-Interleaving PON

Technologies such as the Internet-of-Things and cloud services demand dynamic bandwidth allocation flexibility, which is not offered by the currently deployed solutions. The Bit-Interleaving PON (BiPON) and its cascaded extension the Cascaded Bit-Interleaving PON (CBI-PON) offer a solution that allows to increase bandwidths, reduce power consumption and have a much more flexible dynamic bandwidth allocation scheme. CBI-PON consists of multiple levels of BiPON with different line rates. For each of these line rates, clock-and-data recovery must be performed, which requires a set of different Voltage Controlled Oscillators (VCOs). This paper presents the VCOs designed for the CABINET chip, an implementation of a CBI-PON network device, allowing clock-and-data recovery for 40Gbit/s, 10 Gbit/s and 2.5 Gbit/s line rates.

Solutions for a single carrier 40 Gbit/s downstream long-reach passive optical network

This paper presents a single carrier 40 Gbit/s downstream long-reach passive optical network (LR-PON) topology as candidate for upgrading current fiber infrastructure towards higher data rates. A 100 km LR-PON network was investigated and 2 solutions to overcome chromatic dispersion were proposed. Firstly, a dispersion compensated element is added to compensate the mean length of the feeder fiber. Secondly, an advanced modulation scheme, i.e. 3-level electrical duo-binary is introduced. This scheme has the advantage of allowing lower bandwidth APDs and requires only limited additional electronics. Furthermore, to overcome the inherent discrepancy between aggregated line rate and user rate, and hence the reduced power effciency, the BiPON protocol is added to minimize signal processing at the high line rates.