Pieter Rombouts

A Closed-Loop Digitally Controlled MEMS Gyroscope With Unconstrained Sigma-Delta Force-Feedback

In this paper, we describe the system architecture and prototype measurements of a MEMS gyroscope system with a resolution of 0.025deg/s/ radic(Hz). The architecture makes extensive use of control loops, which are mostly in the digital domain. For the primary mode both the amplitude and the resonance frequency are tracked and controlled. The secondary mode readout is based on unconstrained SigmaDelta force-feedback, which does not require a compensation filter in the loop and thus allows more beneficial quantization noise shaping than prior designs of the same order. Due to the force-feedback, the gyroscope has ample dynamic range to correct the quadrature error in the digital domain. The largely digital setup also gives a lot of flexibility in characterization and testing, where system identification techniques have been used to characterize the sensors. This way, a parasitic direct electrical coupling between actuation and readout of the mass-spring systems was estimated and corrected in the digital domain. Special care is also given to the capacitive readout circuit, which operates in continuous time.

A 13.5-b 1.2-V micropower extended counting A/D converter

This work presents a study of the extended counting technique for a 1.2-V micropower voice-band A/D converter. This extended counting technique is a blend of /spl Sigma//spl Delta/ modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a first-order /spl Sigma//spl Delta/ modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8-/spl mu/m CMOS. With a 1.2-V power supply, it consumes 150 /spl mu/W of power at a 16-kHz Nyquist sampling frequency. The measured peak S/(N+THD) was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about 1.3/spl times/1 mm/sup 2/ of chip area. This is considerably less than a complete /spl Sigma//spl Delta/ modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area.

A double-sampling extended-counting ADC

Extended-counting analog-to-digital conversion combines the accuracy of /spl Sigma//spl Delta/ modulation with the speed of algorithmic conversion. In this paper, a double-sampling technique is introduced for this type of converter. It is based on a variant of the fully floating bilinear integrator. This way, the clock frequency of the converter is almost halved. An experimental converter was designed in a 0.6-/spl mu/m CMOS technology for a bandwidth of 500 kHz at a 3.3-V supply. In the switched-capacitor implementation, the hardware is extensively reused. This way, the converter can be realized with only one operational amplifier. On the other hand, compared to alternative implementations, the amount of switches is increased. These are designed carefully in order not to degrade the performance. The converter converts a sample in 24 clock cycles and achieves a dynamic range of 87 dB. The peak signal-to-noise ratio (SNR) and signal-to-noise-plus-distortion ratio (SNDR) were measured to be 82 and 81 dB, respectively. The power consumption was 28-mW analog and 20-mW digital. The converter core occupies 0.7 mm/sup 2/ including digital logic.

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ.

Web-Based Trainer for Electrical Circuit Analysis

A Web-based system for training electric circuit analysis is presented in this paper. It is centered on symbolic analysis techniques and it not only verifies the students final answer, but it also tracks and coaches him/her through all steps of his/her reasoning path. The system mimics homework assignments, enhanced by immediate personalized feedback. Evaluation data based upon a first trial indicate that this tool is a useful complement to the traditional training approach.

An approach to tackle quantization noise folding in double-sampling /spl Sigma//spl Delta/ modulation A/D converters

/spl Sigma//spl Delta/-modulation is a proven method to realize high- and very high-resolution analog-to-digital converters. A particularly efficient way to implement such a modulator uses double-sampling where the circuit operates during both clock phases of the master-clock. Hence, the sampling frequency is twice the master-clock frequency. Unfortunately, path mismatch between both sampling branches causes a part of the quantization noise to fold from the Nyquist frequency back in the signal band. Therefore, the performance is severely degraded. In this paper, we show that the problem is reduced but not eliminated by employing multibit quantization. Next, we present an in-depth solution for the problem. The approach consists of modifying the quantization noise transfer function of the overall modulator to have one or several zeros at the Nyquist frequency. This way the effect of noise folding can nearly be eliminated. It is shown that this can be implemented by a simple modification of one of the integrators of the overall modulator circuit. Finally, several design examples of single-bit and multibit modulators are discussed.

An Unconstrained Architecture for Systematic Design of Higher Order

Nowadays, SigmaDelta-modulation is a widely used technique for analog-to-digital (A/D) conversion, especially when aiming for high resolutions. While being applied initially for purely electrical A/D converters, its application has been expanded to mixed mechanical-electrical systems. This has led to the use of SigmaDelta force-feedback for digital readout of high-performance inertial sensors. However, compared with their electrical counterpoint, SigmaDelta force-feedback loops often have to deal with three additional issues: 1) an increased stability problem due to phase-lag occurring in the sensor; 2) the injection of relatively high levels of readout noise in the loop; and 3) the lack of degrees-of-freedom of many SigmaDelta force-feedback architectures for implementing an arbitrary noise transfer function. As a result, SigmaDelta force-feedback loops found in literature are designed in a much less systematic way as compared with electrical SigmaDelta modulators. In this paper, we address these issues and propose a new unconstrained architecture. Based on this architecture, we are able to present a systematic approach for designing SigmaDelta force-feedback loops. Additionally, the main strengths and weaknesses of different SigmaDelta force-feedback architectures are discussed.

\Sigma\Delta

This paper presents a high-order double-sampling single-loop /spl Sigma//spl Delta/ modulation analog-to-digital (A/D) converter. The important problem of noise folding in double-sampling circuits is solved here at the architectural level by placing one of the zeros in the modulators noise transfer function at half the sampling frequency instead of in the baseband. The resulting modulator is of fifth order but has the baseband performance of a fourth-order modulator. Through the use of an efficient switched-capacitor implementation, the overall circuit uses only four operational amplifiers and hence, its complexity is similar to that of a fourth-order modulator. An experimental 1-bit modulator was designed for an oversampling ratio of 96 and a bandwidth of 250 kHz at a 3.3-V supply in a conservative 0.8-/spl mu/m standard CMOS process. Due to the double-sampling, the sampling frequency is 48 MHz, although the circuits operate at a clock frequency of only 24 MHz. The circuit achieves a dynamic range of 94 dB. The peak signal-to-noise ratio and signal-to-noise-plus-distortion ratio were measured to be 90 and 86 dB, respectively. The power consumption of the complete circuit including clock drivers and output pad drivers was 43 mW. The analog blocks (opamps, comparators, etc.) consume 30 mW of this total.

Force-Feedback Loops

In this paper we describe the system architecture and prototype measurements of a MEMS gyroscope with a resolution of 0.055°/s/√Hz. Two innovations are presented. The first is the complete migration of control and demodulation tasks to the digital domain. For this purpose, interfacing circuits based on ΣΔ techniques are introduced for both primary and secondary mode. The advantage is that complex analog electronics for tracking the resonant frequency, stabilizing the amplitude of the primary mode oscillation and phase-sensitive demodulation can be replaced by their digital counterpart. A second innovation relates to the ΣΔ force-feedback loop. In previously reported structures a compensation filter is introduced for stabilizing the loop [ 1– 3]. Unfortunately, the compensation filter introduces extra poles and influences the noise-shaping characteristic, which makes the loop difficult to design and optimize. We demonstrate the possibility of obtaining a stable ΣΔ force-feedback loop without an explicit compensation filter.

A 250-kHz 94-dB double-sampling /spl Sigma//spl Delta/ modulation A/D converter with a modified noise transfer function

Capacitor mismatch is the main source of nonlinearity for pipelined analog-to-digital (A/D) converters. Here a digital error-averaging technique is presented to greatly reduce this effect. Compared to the conventional circuit, the new approach requires only one extra digital addition. This allows a very simple and compact implementation. On the other hand, the conversion speed is halved because one conversion now requires two clock cycles instead of one. Therefore this technique is most suitable when moderately high speed combined with high resolution is required.