Arno Vyncke

Fast Synchronization 3R Burst-Mode Receivers for Passive Optical Networks

This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed.

Silicon-organic hybrid (SOH) modulators for intensity-modulation / direct-detection links with line rates of up to 120 Gbit/s

High-speed interconnects in data-center and campus-area networks crucially rely on efficient and technically simple transmission techniques that use intensity modulation and direct detection (IM/DD) to bridge distances of up to a few kilometers. This requires electro-optic modulators that combine low operation voltages with large modulation bandwidth and that can be operated at high symbol rates using integrated drive circuits. Here we explore the potential of silicon-organic hybrid (SOH) Mach-Zehnder modulators (MZM) for generating high-speed IM/DD signals at line rates of up to 120 Gbit/s. Using a SiGe BiCMOS signal-conditioning chip, we demonstrate that intensity-modulated duobinary (IDB) signaling allows to efficiently use the electrical bandwidth, thereby enabling line rates of up to 100 Gbit/s at bit error ratios (BER) of 8.5 × 10-5. This is the highest data rate achieved so far using a silicon-based MZM in combination with a dedicated signal-conditioning integrated circuit (IC). We further show four-level pulse-amplitude modulation (PAM4) at lines rates of up to 120 Gbit/s (BER = 3.2 × 10-3) using a high-speed arbitrary-waveform generator and a 0.5 mm long MZM. This is the highest data rate hitherto achieved with a sub-millimeter MZM on the silicon photonic platform.

Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits

In bang-bang (BB) clock and data recovery circuits (CDR) limit cycles can occur, but these limit cycles are undesired for a good operation of the BB-CDR. Surprisingly, however, a little bit of noise in the system is beneficial, because it will quench the limit cycles. Until now, authors have always assumed that there is enough noise in a BB-CDR such that no limit cycle occurs. In this work, a pseudo-linear analysis based on describing functions is used to investigate this. In particular, the relationship between the input noise and the amplitude of eventual limit cycles is investigated. An important result of the theory is that it allows to quantify the influence of the different loop parameters on the minimal amount of input jitter needed to destroy the limit cycle. Additionally, for the case that there is not enough noise, the worst case amplitude of the limit cycle (which is unavoidable in this case) is quantified as well. The presented analysis exhibits excellent matching with time domain simulations and leads to very simple analytical expressions.

100 Gbit/s serial transmission using a silicon-organic hybrid (SOH) modulator and a duobinary driver IC

100 Gbit/s three-level (50 Gbit/s OOK) signals are generated using a silicon-organic hybrid modulator and a BiCMOS duobinary driver IC at a BER of 8.5×10⁻⁵(<10⁻²). We demonstrate dispersion-compensated transmission over 5 km.

Real-time 100 Gb/s NRZ-OOK transmission with a silicon photonics GeSi electro-absorption modulator

We demonstrate single-wavelength, serial and real-time 100 Gb/s NRZ-OOK transmission over 500 m SSMF with a GeSi EAM implemented on a silicon photonics platform. The device was driven with 2 Vpp without 50 Ω termination, allowing a low-complexity solution for 400 GbE short-reach optical interconnects.

Towards efficient 100 Gb/s serial rate optical interconnects: A duobinary way

Recent advances in integrated opto-electronic devices and front end circuits have made it possible to efficiently transmit very high data rates over optical links for HPC/datacenter applications. This paper reviews our current progress towards serial 100-Gb/s optical interconnects, with emphasis on electrical duobinary (EDB) modulation.

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for its reduced linearity requirements. In this paper, an adaptive sign–sign least mean square equalizer algorithm is developed applicable for an analog transmit-side feed-forward equalizer (FFE) capable of transforming non-return-to-zero modulation to duobinary (DB) modulation at the output of the channel. In addition to the derivation of the update strategy, extra algorithms are developed to cope with the difficult transmit–receive synchronization. Using an analog six tap bit-spaced equalizer, the algorithm is capable of optimizing DB communication of 100Gb/s over 1.5-m Twin-Ax cable. Both simulations and experimental results are presented to prove the capabilities of the algorithm demonstrating automated determination of FFE parameters, such that error-free communication is obtained (BER

An 8-phase 10GHz voltage controlled ring oscillator for 40 Gbit/s BiPON clock-and-data recovery

<10^{-13}

Solutions for a single carrier 40 Gbit/s downstream long-reach passive optical network

using PRBS9).

Fast H.264 intra prediction for network video processing

New technologies such as cloud services and the Internet of Things have led to a demand for higher bandwidths, as well as the need for dynamic bandwidth allocation. This flexible bandwidth is offered by the BiPON protocol. By using BiPON, a significant power consumption reduction can be realized at the receiver side by using a 1:4 sub-sampling clock-and-data recovery circuit (CDR). To realize this CDR, the phase detector needs 8 phases of a 10GHz sampling clock. In this paper, we present the design and measurements of such a VCO, which has a tuning range of 6.57 GHz to 10.61 GHz and a gain of 250 MHz/V, while consuming about 30mW.