Mark A. Beiley

Test structures for characterization and comparative analysis of CMOS image sensors

A set of test structures designed to characterize and compare the performance of CMOS passive and active pixel image sensors is presented. The test structures are deigned so that they can be rapidly ported from one process to another. They are also designed so that individual photodetectors and pixel circuits as well as entire image sensor arrays can be characterized and compared based on: quantum efficiency, spectral response, fixed pattern noise, sensitivity, blooming, input referred read noise, reduction of quantum efficiency caused by silicide/salicide, lag, digital switching noise sensitivity, impact ionization noise sensitivity, dynamic range, and temperature dependency of all measured parameters. Four test chips that include a variety of these structures have been built in two different 0.35 micrometer CMOS processes. The test chips include nineteen types of individual photodetectors and thirty eight types of 64 by 64 pixel arrays. The test methodology and preliminary test results from these chips are presented.

A design methodology for the I/O power supply of next generation packaging

The method of three-dimensional I/O power modeling is reviewed in detail based on the learning from the previous one-dimensional and two-dimensional models. This paper covers the latest development of next generation microprocessor I/O power models and the adoption of a new three-dimensional modeling methodology to meet the challenging design requirements of a high performance signal bus with short turn-around times. The paper also presents a new technique of using damping resistors to attenuate the high frequency noise on the I/O supply.