Boyd A. Fowler

A 640/spl times/512 CMOS image sensor with ultra wide dynamic range floating-point pixel-level ADC

The dynamic range of an image sensor is often not wide enough to capture scenes with both high lights and dark shadows. A 640/spl times/512 image sensor with Nyquist rate pixel level ADC implemented in a 0.35 /spl mu/m CMOS technology shows how a pixel level ADC enables flexible efficient implementation of multiple sampling. Since pixel values are available to the ADCs at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected without the long readout time of APS. Typically, hundreds of nanoseconds of settling time per row are required for APS readout. In contrast, using pixel level ADC, digital data is read out at fast SRAM speeds. This demonstrates another fundamental advantage of pixel level ADC-the ability to programmably widen dynamic range with no loss in SNR.

Analysis of temporal noise in CMOS photodiode active pixel sensor

Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise.

A 640×512 CMOS image sensor with ultra wide dynamic range floating-point pixel-level ADC

Analysis results demonstrate that multiple sampling can achieve consistently higher signal-to-noise ratio at equal or higher dynamic range than using other image sensor dynamic range enhancement schemes such as well capacity adjusting. Implementing multiple sampling, however, requires much higher readout speeds than can be achieved using typical CMOS active pixel sensor (APS). This paper demonstrates, using a 640 512 CMOS image sensor with 8-b bit-serial Nyquist rate analog-to- digital converter (ADC) per 4 pixels, that pixel-level ADC enables a highly flexible and efficient implementation of multiple sam- pling to enhance dynamic range. Since pixel values are available to the ADCs at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected and read out at fast SRAM speeds. By sampling at exponentially increasing exposure times, pixel values with binary floating-point resolution can be obtained. The 640 512 sensor is implemented in 0.35- m CMOS technology and achieves 10.5 10.5 m pixel size at 29% fill factor. Characterization techniques and measured quantum efficiency, sensitivity, ADC transfer curve, and fixed-pattern noise are presented. A scene with measured dynamic range exceeding 10 000 : 1 is sampled nine times to obtain an image with dynamic range of 65 536 : 1. Limits on achievable dynamic range using multiple sampling are presented.

A Nyquist-rate pixel-level ADC for CMOS image sensors

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320/spl times/256 sensor using the MCBS ADC is described. The chip measures 4.14/spl times/5.16 mm/sup 2/. It achieves 10/spl times/10 /spl mu/m/sup 2/ pixel size at 28% fill factor in 0.35 /spl mu/m CMOS technology. Each 2/spl times/2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively.

A CMOS area image sensor with pixel-level A/D conversion

Charge-coupled devices (CCD) are at present the most widely used technology for implementing area image sensors. However, they suffer from low yields, consume too much power, and are plagued with SNR limitations due to the shifting and detection of analog charge packets, and the fact that data is communicated off chip in analog form. This paper describes an area image sensor that can potentially circumvent the limitations of CCDs and their alternatives. It uses a standard CMOS process and can therefore be manufactured with high yield. Digital circuitry for control and signal processing can be integrated with the sensor. Moreover, CMOS technology advances such as scaling and extra layers of metal can be used to improve pixel density and sensor performance. The analog image data is immediately converted to digital at each pixel using a one-bit sigma-delta modulator. The use of sigma-delta modulation allows the data-conversion circuitry to be simple and insensitive to process variations. A global shutter provides variable light input attenuation to achieve wide dynamic range. Data is communicated off chip in a digital form, eliminating the SNR degradation of analog data communication. To demonstrate the viability of the approach, an area image sensor chip is fabricated in a 1.2 /spl mu/m CMOS technology. The device consists of an array of 64x64 pixel blocks, a clock driver, a 6:64 row address decoder, 64 latched sense amplifiers, and 16 4:1 column multiplexers. The chip also contains data compression circuitry.<<ETX>>

Modeling and estimation of FPN components in CMOS image sensors

Fixed pattern noise (FPN) for a CCD sensor is modeled as a sample of a spatial white noise process. This model is, however, not adequate for characterizing FPN in CMOS sensors, since the redout circuitry of CMOS sensors and CCDs are very different. The paper presents a model for CMOS FPN as the sum of two components: a column and a pixel component. Each component is modeled by a first order isotropic autoregressive random process, and each component. Each component is modeled by a first order isotropic autoregressive random process, and each component is assumed to be uncorrelated with the other. The parameters of the processes characterize each component of the FPN and the correlations between neighboring pixels and neighboring columns for a batch of sensor. We show how to estimate the model parameters from a set of measurements, and report estimates for 64 X 64 passive pixel sensor (PPS) and active pixel sensor (APS) test structures implemented in a 0.35 micron CMOS process. High spatial correlations between pixel components were measured for the PPS structures, and between the column components in both PPS and APS. The APS pixel components were uncorrelated.

Pixel Level Processing — Why, What, and How?

Pixel level processing promises many significant advantages including high SNR, low power, and the ability to adapt image capture and processing to different environments by processing signals during integration. However, the severe limitation on pixel size has precluded its mainstream use. In this paper we argue that CMOS technology scaling will make pixel level processing increasingly popular. Since pixel size is limited primarily by optical and light collection considerations, as CMOS technology scales, an increasing number of transistors can be integrated at the pixel. We first demonstrate that our argument is supported by the evolution of CMOS image sensor from PPS to APS. We then briefly survey existing work on analog pixel level processing an d pixel level ADC. We classify analog processing into intrapixel and interpixel. Intrapixel processing is mainly used to improve sensor performance, while interpixel processing is used to perform early vision processing. We briefly describe the operation and architecture of our recently developed pixel level MCBS ADC. Finally we discuss future directions in pixel level processing. We argue that interpixel analog processing is not likely to become mainstream even for computational sensors due to the poor scaling popular since it minimizes analog processing, and requires only simple and imprecise circuits to implement. We then discuss the inclusion of digital memory and interpixel digital processing in future technologies to implement programmable digital pixel sensors.

A Nyquist rate pixel level ADC for CMOS image sensors

A Nyquist rate Multi-Channel bit serial (MCBS) ADC using successive comparisons is presented. The ADC is suited to pixel level implementation in a CMOS image sensor. It comprises a 1-bit comparator/latch pair per 4 pixels and a DAC/controller shared by all pixels. A CMOS 320/spl times/240 sensor using the MCBS ADC is described. It achieves 8.9/spl times/8.9 /spl mu/m pixel size at 25% fill factor in 0.35 /spl mu/m CMOS technology. Measured INL/DNL for the ADC are 2.3/1.2 LSB at 8-bit. Gain/offset FPN due to ADC are 0.24%/0.2%.

A 128/spl times/128 pixel CMOS area image sensor with multiplexed pixel level A/D conversion

A 128/spl times/128 pixel CMOS area image sensor with a sigma-delta A/D Converter shared within each group of 2/spl times/2 pixels is described. Each pixel comprises a photodiode and 4 MOSFETs and occupies 20.8 /spl mu/m/spl times/19.8 /spl mu/m with a fill factor of 30% in a 0.8 /spl mu/m three layer metal one layer poly CMOS process. At 3.3 V, the dynamic range is >83 dB, the dissipation is <1 mW and the fixed pattern noise is /spl ap/1%.

Low-noise readout using active reset for CMOS APS

Pixel reset noise sets the fundamental detection limit on photodiode based CMOS image sensors. Reset noise in standard active pixel sensor (APS) is well understood and is of order kT/C. In this paper we present a new technique for resetting photodiodes, called active reset, which reduces reset noise without adding lag. Active reset can be applied to standard APS. Active reset uses bandlimiting and capacitive feedback to reduce reset noise. This paper discusses the operation of an active reset pixel, and presents an analysis of lag and noise. Measured results from a 6 transistor per pixel 0.35 micrometers CMOS implementation are presented. Measured results show that reset noise can be reduced to less than kT/18C using active reset. We find that theory simulation and measured results all match closely.