David X. D. Yang

A 640/spl times/512 CMOS image sensor with ultra wide dynamic range floating-point pixel-level ADC

The dynamic range of an image sensor is often not wide enough to capture scenes with both high lights and dark shadows. A 640/spl times/512 image sensor with Nyquist rate pixel level ADC implemented in a 0.35 /spl mu/m CMOS technology shows how a pixel level ADC enables flexible efficient implementation of multiple sampling. Since pixel values are available to the ADCs at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected without the long readout time of APS. Typically, hundreds of nanoseconds of settling time per row are required for APS readout. In contrast, using pixel level ADC, digital data is read out at fast SRAM speeds. This demonstrates another fundamental advantage of pixel level ADC-the ability to programmably widen dynamic range with no loss in SNR.

Pixel Level Processing — Why, What, and How?

Pixel level processing promises many significant advantages including high SNR, low power, and the ability to adapt image capture and processing to different environments by processing signals during integration. However, the severe limitation on pixel size has precluded its mainstream use. In this paper we argue that CMOS technology scaling will make pixel level processing increasingly popular. Since pixel size is limited primarily by optical and light collection considerations, as CMOS technology scales, an increasing number of transistors can be integrated at the pixel. We first demonstrate that our argument is supported by the evolution of CMOS image sensor from PPS to APS. We then briefly survey existing work on analog pixel level processing an d pixel level ADC. We classify analog processing into intrapixel and interpixel. Intrapixel processing is mainly used to improve sensor performance, while interpixel processing is used to perform early vision processing. We briefly describe the operation and architecture of our recently developed pixel level MCBS ADC. Finally we discuss future directions in pixel level processing. We argue that interpixel analog processing is not likely to become mainstream even for computational sensors due to the poor scaling popular since it minimizes analog processing, and requires only simple and imprecise circuits to implement. We then discuss the inclusion of digital memory and interpixel digital processing in future technologies to implement programmable digital pixel sensors.

Comparative analysis of SNR for image sensors with enhanced dynamic range

Dynamic range is a critical figure of merit for image sensors. Often a sensor with higher dynamic range is regarded as higher quality than one with lower dynamic range. For CCD and CMOS sensors operating in the integration mode the sensor SNR monotonically increases with the signal. Therefore, a sensor with higher dynamic range, generally, produces higher quality images than one with lower dynamic range. This, however, is not necessarily the case when dynamic range enhancement schemes are used. For example, suing the well capacity adjusting scheme dynamic range is enhanced but at the expense of substantial degradation in SNR. On the other hand, using multiple sampling dynamic range can be enhanced without degrading SNR. Therefore, even if both schemes achieve the same dynamic range the latter can produce higher image quality than the former. The paper provides a quantitative framework for comparing SNR for image sensors with enhanced dynamic range. We introduce a simple model to describe the sensor output response as a function of the photogenerate signal, dark signal, and noise for sensors operation in integration mode with and without dynamic range enhancement schemes. We use the model to quantify and compare dynamic range and SNR for three sensor operation modes, integration with shuttering, using the well capacity adjusting scheme, and using multiple sampling.

A Nyquist rate pixel level ADC for CMOS image sensors

A Nyquist rate Multi-Channel bit serial (MCBS) ADC using successive comparisons is presented. The ADC is suited to pixel level implementation in a CMOS image sensor. It comprises a 1-bit comparator/latch pair per 4 pixels and a DAC/controller shared by all pixels. A CMOS 320/spl times/240 sensor using the MCBS ADC is described. It achieves 8.9/spl times/8.9 /spl mu/m pixel size at 25% fill factor in 0.35 /spl mu/m CMOS technology. Measured INL/DNL for the ADC are 2.3/1.2 LSB at 8-bit. Gain/offset FPN due to ADC are 0.24%/0.2%.

Techniques for pixel-level analog-to-digital conversion

Two techniques for performing pixel level analog to digital conversion (ADC) are reviewed. The first is an over-sampling technique which uses a one bit first order (Sigma) (Delta) modulator for each 2 X 2 block of pixels to directly convert photocharge to bits. Each modulator is implemented using 17 transistors. The second technique is a Nyquist rate multi-channel-bit-serial (MCBS) ADC. The technique use successive comparisons to convert the pixel voltage to bits. Results obtained from implementations of these ADC techniques are presented. The techniques are compared based on size, charge handling capacity, FPN, noise sensitivity, data throughput, quantization, memory/processing, and power dissipation requirements for both visible an dIR imagers. From the comparison it appears that the (Sigma) (Delta) ADC is better suited to IR imagers, while the MCBS ADC is better suited to imagers in the visible range.

Test structures for characterization and comparative analysis of CMOS image sensors

A set of test structures designed to characterize and compare the performance of CMOS passive and active pixel image sensors is presented. The test structures are deigned so that they can be rapidly ported from one process to another. They are also designed so that individual photodetectors and pixel circuits as well as entire image sensor arrays can be characterized and compared based on: quantum efficiency, spectral response, fixed pattern noise, sensitivity, blooming, input referred read noise, reduction of quantum efficiency caused by silicide/salicide, lag, digital switching noise sensitivity, impact ionization noise sensitivity, dynamic range, and temperature dependency of all measured parameters. Four test chips that include a variety of these structures have been built in two different 0.35 micrometer CMOS processes. The test chips include nineteen types of individual photodetectors and thirty eight types of 64 by 64 pixel arrays. The test methodology and preliminary test results from these chips are presented.

Method for estimating quantum efficiency for CMOS image sensors

The standard method for measuring QE for a CCD sensor is not adequate for CMOS APS since it does not take into consideration the random offset, gain variations, and nonlinearity introduced by the APS readout circuits. The paper presents a new method to accurately estimate QE of an APS. Instead of varying illumination as in the CCD method, illumination is kept constant and the pixel output is continuously observed - sampling at regular intervals. This makes it possible to eliminate random offset. The experiment is repeated multiple times to obtain good estimates of the pixel output mean and variance at each sample time. The sensor response is approximated by a piecewise linear function and using the Poisson statistics of shot noise gain, charge and read noise are estimated for each line segment. This procedure is repeated at no illumination so that dark charge may be estimated and subtracted from the total charge estimates. The method can also be used to estimate readout noise and gain FPN. Results from 64 X 64 pixel APS test structures implemented in a 0.35 micrometers CMOS process are reported. Using 6 different chips and 16 pixels per chip QE equals 0.37, gain FPN equals 2 percent, dark charge equals 832e-, and readout noise equals 40e-, are estimated.

Characterization of CMOS image sensors with Nyquist rate pixel-level ADC

Techniques for characterizing CCD imagers have been developed over many years. These techniques have been recently modified and extended to CMOS PPS and APS imagers. With the scaling of CMOS technology, an increasing number of transistors can be added to each pixel. A promising direction to utilize these transistors is to perform pixel level ADC. The authors have designed and prototyped two imagers with pixel level Nyquist rate ADC. The ADCs operate in parallel and output data one bit at a time. The data is read out of the imager array one bit plane at a time in a manner similar to a digital memory. Existing characterization techniques could not be directly used for these imagers, however, since there is no facility to read out the analog pixel values before ADC, and the ADC resolution is limited to only 8 bits. Fortunately, the ADCs are fully testable electrically without the need for any light or optics. This makes it possible obtain the ADC transfer curve, which greatly simplifies characterization. In this paper we describe how we characterize our pixel level ADC imagers. To estimate QE, we measure the imager photon to DN transfer curve and the ADC transfer curve. We find that both curves are quite linear.Using an estimate of the sense node capacitance we then estimate sensitivity, and QE. To estimate FPN we model it as an outcome of the sum of two uncorrelated random processes, one representing the ADC FPN, and the other representing the photodetector FPN, and develop estimators for the model parameters form imager data under uniform illumination. We report characterization result for a 640 by 512 imager, which was fabricated in a 0.35 micrometers standard digital CMOS process.