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Dive into the research topics where Mark A. Durlam is active.

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Featured researches published by Mark A. Durlam.


IEEE Transactions on Magnetics | 2005

A 4-Mb toggle MRAM based on a novel bit and switching method

Brad Engel; Johan Åkerman; Brian R. Butcher; Renu W. Dave; M. DeHerrera; Mark A. Durlam; G. Grynkewich; Jason Allen Janesky; Srinivas V. Pietambaram; N. D. Rizzo; Jon M. Slaughter; Kenneth H. Smith; Jijun Sun; Saied N. Tehrani

A 4-Mb magnetoresistive random access memory (MRAM) with a novel magnetic bit cell and toggle switching mode is presented. The circuit was designed in a five level metal, 0.18-mum complementary metal-oxide-semiconductor process with a bit cell size of 1.55 mum2. The new bit cell uses a balanced synthetic antiferromagnetic free layer and a phased write pulse sequence to provide robust switching performance with immunity from half-select disturbs. This switching mode greatly improves the operational performance of the MRAM as compared to conventional MRAM. A detailed description of this 4-Mb toggle MRAM is presented


ieee international magnetics conference | 2000

Recent developments in magnetic tunnel junction MRAM

Saied N. Tehrani; Bradley N. Engel; Jon M. Slaughter; Eugene Youjun Chen; M. DeHerrera; Mark A. Durlam; P. Naji; R. Whig; Jason Allen Janesky; J. Calder

We summarize our progress on Magnetoresistive Random Access Memory (MRAM) based on Magnetic Tunnel Junctions (MTJ). We have demonstrated MTJ material in the 1-1000 k/spl Omega/-/spl mu/m/sup 2/ range with MR values above 40%. The switching characteristics are mainly governed by the magnetic shape anisotropy that arises from the element boundaries. The switching repeatability, as well as hard axis selectability, are shown to be dependent on both shape and aspect ratio. MTJ memory elements were successfully integrated with 0.6 /spl mu/m CMOS technology, achieving read and program address access times of 14 ns in a 256/spl times/2 MRAM.


IEEE Transactions on Device and Materials Reliability | 2004

Demonstrated reliability of 4-mb MRAM

Johan Åkerman; Philip Brown; M. DeHerrera; Mark A. Durlam; Earl D. Fuchs; D. Gajewski; Mark Griswold; Jason Allen Janesky; Joseph J. Nahas; Saied N. Tehrani

The successful commercialization of MRAM will rely on providing customers with a robust and reliable memory product. The intrinsic reliability of magnetoresistive tunnel junction (MTJ) memory bits and the metal interconnect system of MRAM are two areas of great interest due to the new materials involved in this emerging technology. Time dependent dielectric breakdown (TDDB) and resistance drift were the two main failure mechanisms identified for intrinsic memory bit reliability. Results indicated that a lifetime over 10 years is achievable under the operating condition. For metal interconnect system, the initial results of Cu with magnetic cladding have met the reliability performance of typical nonclad Cu backend process in electromigration (EM) and iso-thermal annealing (ITA). Finally data retention is demonstrated over times orders of magnitude longer than 10 years.


international electron devices meeting | 2005

High speed toggle MRAM with mgO-based tunnel junctions

Jon M. Slaughter; Renu W. Dave; Mark A. Durlam; G. Kerszykowski; Kenneth H. Smith; K. Nagel; B. Feil; J. Calder; M. DeHerrera; B. Garni; Saied N. Tehrani

We report here the first integration of a new generation of high magnetoresistance-ratio (MR) magnetic tunnel junction (MTJ) material with a 90 nm CMOS front-end logic process. This new material, with MgO tunnel barriers, significantly increased the read signal over standard AlOx-based material. The 90 nm CMOS test vehicle has 8 kb arrays of 1T1MTJ memory cells with two orthogonal program lines oriented at 45deg from the bit easy axis for toggle switching. Read and toggle-write operations are demonstrated


international conference on ic design and technology | 2007

MRAM Memory for Embedded and Stand Alone Systems

Mark A. Durlam; Y. Chung; M. DeHerrera; Bradley N. Engel; G. Grynkewich; B. Martino; Bich-Yen Nguyen; J. Salter; P. Shah; J.M. Slaughter

Magnetoresistive random access memory (MRAM) is based on magnetic tunnel junction devices integrated with standard CMOS resulting in high-speed read and write, unlimited endurance, and the highest reliability of any non-volatile memory. MRAM is a unique memory technology in that the module is inserted late in the manufacturing process, making MRAM highly compatible with advanced processing. The manufacturing flexibility of MRAM makes it an attractive choice for embedded and stand alone memory systems.


Magnetoelectronics | 2004

Chapter 5 – Magnetic tunnel junction based magnetoresistive random access memory

Johan { AA}kerman; M. DeHerrera; Mark A. Durlam; Brad Engel; Jason Allen Janesky; Fred Mancoff; Jon M. Slaughter; Saied N. Tehrani

Publisher Summary This chapter presents the salient features of state-of-the-art magnetic tunnel junctions (MTJ)-based magnetoresistive random access memory (MRAM). The chapter provides a description of 0.18 um MRAM technology and its implementation in a 1 Mb memory array. MRAM bit size scaling and challenges associated with continued miniaturization are discussed. A novel switching approach with significantly improved scaling properties is also presented. The ability to scale the MRAM bit cell to smaller dimensions is essential for MRAM to be a competitive memory technology. As the bit size is reduced, write performance could be affected by several parameters—switching field, write line field generation, bit-to-bit variation of the switching field within an array, hard-axis field response, susceptibility to thermal fluctuations, and magnetostatic interactions between neighboring bits. Magnetostatic interactions between neighboring bits must also be considered as the size of the bit cell is reduced and the density of the array is increased. A given bit experiences different values and configurations of stray fields depending on the details of the magnetization directions of surrounding bits. Savtchenko switching relies on the unique behavior of a synthetic antiferromagnet (SAF) free layer that is formed from two ferromagnetic layers separated by a nonmagnetic coupling spacer layer. The moments of the balanced SAF free-layer are antiparallel in zero-field and the coupled system therefore responds to an applied magnetic field in a manner that is different from the single ferromagnetic layer of conventional MRAM.


international symposium on vlsi technology, systems, and applications | 2007

Toggle MRAM: A highly-reliable Non-Volatile Memory

Mark A. Durlam; B. Craigo; M. DeHerrera; Bradley N. Engel; G. Grynkewich; B. Huang; Jason Allen Janesky; M. Martin; B. Martino; J. Salter; Jon M. Slaughter; L. Wise; Saied N. Tehrani

Magnetoresistive Random Access Memory (MRAM) is based on magnetic tunnel junction devices integrated with standard CMOS, resulting in high-speed read and write, unlimited endurance, and the highest reliability of any non-volatile memory. The first commercially available MRAM product, Freescales 4Mb MR2A16A Toggle MRAM, was released for production in 2006 and is now in volume production. In this paper we provide an overview of Freescales MRAM technology and describe the performance and reliability attributes of the MR2A16A.


symposium on vlsi technology | 2005

90nm toggle MRAM array with 0.29/spl mu/m/sup 2/ cells

Mark A. Durlam; T. Andre; P. Brown; J. Calder; J. Chan; R. Cuppens; R.W. Dave; T. Ditewig; M. DeHerrera; B.N. Engel; B. Feil; C. Frey; D. Galpin; B. Garni; G. Grynkewich; J. Janesky; G. Kerszykowski; M. Lien; J. Martin; J. Nahas; K. Nagel; K. Smith; C. Subramanian; J.J. Sun; J. Tamim; R. Williams; L. Wise; S. Zoll; F. List; R. Fournel

A 90nm magnetoresistive random access memory (MRAM) based on the toggle switching mode has been successfully demonstrated for the first time in a 90nm CMOS process. The MRAM memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) with 0.29/spl mu/m/sup 2/bit cell. The results of the 4k bit array demonstrate scalability of MRAM to 90nm technology.


Archive | 2001

MTJ MRAM series-parallel architecture

Peter K. Naji; M. DeHerrera; Mark A. Durlam


Archive | 2005

3-d inductor and transformer devices in mram embedded integrated circuits

Young Sir Chung; Robert W. Baird; Mark A. Durlam; Bradley N. Engel

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M. DeHerrera

Freescale Semiconductor

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