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Dive into the research topics where Brian R. Butcher is active.

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Featured researches published by Brian R. Butcher.


Proceedings of the IEEE | 2003

Magnetoresistive random access memory using magnetic tunnel junctions

Saied N. Tehrani; Jon M. Slaughter; Mark DeHerrera; Brad N. Engel; Nicholas D. Rizzo; John Salter; Mark Durlam; Renu W. Dave; Jason Allen Janesky; Brian R. Butcher; Kenneth C. Smith; G. Grynkewich

Magnetoresistive random access memory (MRAM) technology combines a spintronic device with standard silicon-based microelectronics to obtain a combination of attributes not found in any other memory technology. Key attributes of MRAM technology are nonvolatility and unlimited read and write endurance. Magnetic tunnel junction (MTJ) devices have several advantages over other magnetoresistive devices for use in MRAM cells, such as a large signal for the read operation and a resistance that can be tailored to the circuit. Due to these attributes, MTJ MRAM can operate at high speed and is expected to have competitive densities when commercialized. In this paper, we review our recent progress in the development of MTJ-MRAM technology. We describe how the memory operates, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled our recent demonstration of a 1-Mbit memory chip. Important memory attributes are compared between MRAM and other memory technologies.


IEEE Transactions on Magnetics | 2005

A 4-Mb toggle MRAM based on a novel bit and switching method

Brad Engel; Johan Åkerman; Brian R. Butcher; Renu W. Dave; M. DeHerrera; Mark A. Durlam; G. Grynkewich; Jason Allen Janesky; Srinivas V. Pietambaram; N. D. Rizzo; Jon M. Slaughter; Kenneth H. Smith; Jijun Sun; Saied N. Tehrani

A 4-Mb magnetoresistive random access memory (MRAM) with a novel magnetic bit cell and toggle switching mode is presented. The circuit was designed in a five level metal, 0.18-mum complementary metal-oxide-semiconductor process with a bit cell size of 1.55 mum2. The new bit cell uses a balanced synthetic antiferromagnetic free layer and a phased write pulse sequence to provide robust switching performance with immunity from half-select disturbs. This switching mode greatly improves the operational performance of the MRAM as compared to conventional MRAM. A detailed description of this 4-Mb toggle MRAM is presented


Archive | 2007

Electronic device including a magneto-resistive memory device and a process for forming the electronic device

Phillip G. Mather; Sanjeev Aggarwal; Brian R. Butcher; Renu W. Dave; Frederick B. Mancoff; Nicholas D. Rizzo


Archive | 2003

Methods for fabricating MRAM device structures

Gregory W. Grynkewich; Brian R. Butcher; Mark Durlam; Kelly W. Kyler; Kenneth H. Smith; Clarence J. Tracy


Archive | 2005

Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices

Gregory W. Grynkewich; Brian R. Butcher; Mark Durlam; Kelly W. Kyler; Charles A. Synder; Kenneth H. Smith; Clarence J. Tracy; Richard G. Williams


Archive | 2002

Cladded conductor for use in a magnetoelectronics device and method for fabricating the same

Mark A. Durlam; Jeffrey H. Baker; Brian R. Butcher; M. DeHerrera; John J. D'urso; Earl D. Fuchs; Gregory W. Grynkewich; Kelly W. Kyler; Jaynal A. Molla; J. Jack Ren; Nicholas D. Rizzo


Archive | 2004

Magnetoresistive random access memory devices and methods for fabricating the same

Gregory W. Grynkewich; Brian R. Butcher; Mark Durlam; Clarence J. Tracy


Archive | 2005

Method for fabricating a flux concentrating system for use in a magnetoelectronics device

Thomas V. Meixner; Gregory W. Grynkewich; Jaynal A. Molla; J. Jack Ren; Richard G. Williams; Brian R. Butcher; Mark A. Durlam


Archive | 2002

Method of fabricating a self-aligned via contact for a magnetic memory element

Kelly W. Kyler; Saied N. Tehrani; John J. D'urso; Gregory W. Grynkewich; Mark Durlam; Brian R. Butcher


Archive | 2006

Magnetic tunnel junction memory and method with etch-stop layer

Kenneth H. Smith; Brian R. Butcher; Gregory W. Grynkewich; Srinivas V. Pietambaram; Nicholas D. Rizzo

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J. Jack Ren

Freescale Semiconductor

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