Mark Andrew Bickerstaff

A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless

A 24Mb/s 3GPP-HSDPA radix-4 logMAP turbo decoder is designed for 3G data terminals. It features an approximate radix-4 logsum circuit to achieve 145MHz operation. Power is reduced using 1/2-iteration early termination and extrinsics are interleaved in companded format. The decoder core is 14.5mm/sup 2/ in 0.18/spl mu/m CMOS.

A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A 3GPP-compliant 4.1 Mb/s channel decoder supports data and voice calls in a unified Turbo/Viterbi architecture with hardware interleaver memory and pattern computation. The 9 mm/sup 2/ chip in 0.18 /spl mu/m 1.8 V 6LM CMOS operates at 110 MHz and consumes 306 mW when decoding 2 Mb/s data and voice calls.

System architecture and ASICs for a MIMO 3GPP-HSDPA receiver

Multiple-input multiple-output (MIMO) technology has been proposed for the high speed downlink packet access (HSDPA) extension to the 3GPP mobile wireless standard to achieve high data throughput with significantly increased spectral efficiency. Data is encoded, interleaved, spread and transmitted over multiple antennas. This paper presents an architecture for a baseband MIMO HSDPA receiver. The architecture is based on two prototype silicon devices that perform MIMO detection and turbo decoding. System simulations prove the high performance potential of the MIMO proposal for HSDPA. Furthermore, the acceptable complexity of both devices demonstrates the practicality of a single chip solution for an HSDPA MIMO receiver.

Integrated circuits for channel coding in 3G cellular mobile wireless systems

Error control coding is a key element of any digital wireless communication system, minimizing the effects of noise and interference on the transmitted signal at the physical layer. In 3G mobile cellular wireless systems, error control coding must accommodate both voice and data users, whose requirements vary considerably in terms of latency, throughput, and the impact of errors on the user application. At the base station, dedicated hardware or readily reconfigurable components are needed to address the concurrent coding and decoding demands of a large number of users with different call parameters. In contrast, the encoder and decoder at the user equipment (UE) are dedicated to a single call setup which changes infrequently. In designing encoder and decoder solutions for 3G wireless systems, not only are the performance issues important, but also the costs. Cellular wireless infrastructure manufacturers need to reduce costs, maximize system reuse, and increase flexibility in order to compete in the market. Furthermore, future-proofing a network is a primary concern due to the high cost of deployment. For the UE, power consumption (battery life) and size are key constraints in addition to manufacturing costs. This article considers the 3G decoder design problem and, using case studies, describes two 3G decoder solutions using ASICs. The first device is targeted for base station deployment and is based on a unified architecture for convolutional and turbo decoding. The second device is a dedicated high-speed radix-4 logMAP turbo decoder targeted for UE, motivated by the requirements for high-speed downlink packet access. Both devices have been fabricated in 0.18 /spl mu/m CMOS technology, and while optimized for either base station or UE, may be used in both applications.

An 8-user UMTS channel unit processor for 3GPP base station applications

We present a multi-user W-CDMA baseband channel unit processor ASIC for cellular base station applications. The ASIC is compliant with the 3GPP/UMTS standard and exceeds 3GPP minimum requirements for high-speed data by 2.1 to 6.35 dB. It supports up to 8 users simultaneously, with a mix of voice and data services and a maximum uplink data rate of 384 kbps. The ASIC implements preamble detection, searching, RAKE-finger demodulation, channel coding/decoding for voice and data services, and transmission functions. It is coupled to a DSP to form a complete channel element for 8 users. The ASIC has 1.88 M gates plus 2.7 Mbits of SRAM in a 0.16 /spl mu/m CMOS process at 61.44 MHz.

An eight-user UMTS channel unit Processor for 3GPP base station applications

We present a multi-user W-CDMA baseband channel unit processor for cellular base station applications. The ASIC is compliant with the 3GPP/UMTS standard and exceeds 3GPP minimum requirements for high-speed data by 2.2-6.2 dB. It supports up to eight users simultaneously, with a mix of voice and data services and a maximum uplink data rate of 384 kb/s and maximum downlink data rate of 2 Mb/s. The ASIC implements preamble detection, searching, demodulation RAKE-finger processing, channel coding/decoding for voice and data services, and transmission functions. It is coupled to a DSP to form a complete channel element for eight users.

DSP systems for next-generation mobile wireless infrastructure

Cellular mobile systems are evolving to offer enhanced packet data services at increased data rates. Emerging standards like GPRS, EDGE, UMTS and CDMA2000 promise high-speed Internet access and multimedia applications on an anywhere, anytime basis. Whereas most research efforts focus on portable handsets, this paper discusses the implications of these standards on the design of next-generation mobile infrastructure systems. Basestations (BTS) will require flexible, low cost integrated solutions that are capable of supporting several-standards. Software radio architectures will see increased deployment in these systems and this paper describes DSP-only and hybrid DSP+IP Core approaches. We argue that the implementation efficiency of the Viterbi algorithm and the SOVA and LOG-MAP variants will become a differentiating factor for next-generation wireless communications-particularly in those employing programmable DSP devices.