David Garrett

Silicon complexity for maximum likelihood MIMO detection using spherical decoding

Multiple-input multiple-output (MIMO) wireless systems increase spectral efficiency by transmitting independent signals on multiple transmit antennas in the same channel bandwidth. The key to using MIMO is in building a receiver that can decorrelate the spatial signatures on the receiver antenna array. Original MIMO detection schemes such as the vertical Bell Labs layered space-time (VBLAST) detector use a nulling and cancellation process for detection that is sub-optimal as compared to constrained maximum likelihood (ML) techniques. This paper presents a silicon complexity analysis of ML search techniques for MIMO as applied to the HSDPA extension of UMTS. For MIMO constellations of 4/spl times/4 QPSK or lower, it is possible to perform an exhaustive ML search in todays silicon technologies. When the search complexity exceeds technology limits for high complexity MIMO constellations, it is possible to apply spherical decoding techniques to achieve near-ML performance. The paper presents an architecture for a 4/spl times/4 16QAM MIMO spherical decoder with soft outputs that achieves 38.8 Mb/s over a 5-MHz channel using only approximately 10 mm/sup 2/ in a 0.18-/spl mu/m CMOS process.

A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless

A 24Mb/s 3GPP-HSDPA radix-4 logMAP turbo decoder is designed for 3G data terminals. It features an approximate radix-4 logsum circuit to achieve 145MHz operation. Power is reduced using 1/2-iteration early termination and extrinsics are interleaved in companded format. The decoder core is 14.5mm/sup 2/ in 0.18/spl mu/m CMOS.

A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A 3GPP-compliant 4.1 Mb/s channel decoder supports data and voice calls in a unified Turbo/Viterbi architecture with hardware interleaver memory and pattern computation. The 9 mm/sup 2/ chip in 0.18 /spl mu/m 1.8 V 6LM CMOS operates at 110 MHz and consumes 306 mW when decoding 2 Mb/s data and voice calls.

Energy efficient turbo decoding for 3G mobile

The requirement of turbo decoding in 3G wireless standards has forced handset designers to consider power consumption issues in their implementations. The phenomenal performance of turbo codes comes at the expense of computation. Primarily this paper looks at methods of substantially reducing the power consumption for the decoding operation, making it feasible to integrate turbo decoders into a low power handset. The techniques presented include early termination of the turbo process, encoding of extrinsic information to reduce the memory size, and disabling portions of the MAP algorithm when the results will not affect the decoded output. The net result of these techniques is almost a 70% reduction in power over a fixed 6 iteration, 8-state baseline turbo decoder at 2 dB of signal to noise ratio (SNR).

System architecture and ASICs for a MIMO 3GPP-HSDPA receiver

Multiple-input multiple-output (MIMO) technology has been proposed for the high speed downlink packet access (HSDPA) extension to the 3GPP mobile wireless standard to achieve high data throughput with significantly increased spectral efficiency. Data is encoded, interleaved, spread and transmitted over multiple antennas. This paper presents an architecture for a baseband MIMO HSDPA receiver. The architecture is based on two prototype silicon devices that perform MIMO detection and turbo decoding. System simulations prove the high performance potential of the MIMO proposal for HSDPA. Furthermore, the acceptable complexity of both devices demonstrates the practicality of a single chip solution for an HSDPA MIMO receiver.

A 28.8 Mb/s 4/spl times/4 MIMO 3G high-speed downlink packet access receiver with normalized least mean square equalization

A receiver for high-speed downlink packet access supporting 28.8 Mb/s using QPSK over a 5 MHz frequency selective 4/spl times/4 MIMO wireless channel (5.76 b/s/Hz). A key feature is the normalized least mean squares space-time equalizer using a pilot correlator for more accurate adaptation. Fabricated in 0.18 /spl mu/m 6M CMOS, the core of the chip covers an 11.6 mm/sup 2/ area.

Integrated circuits for channel coding in 3G cellular mobile wireless systems

Error control coding is a key element of any digital wireless communication system, minimizing the effects of noise and interference on the transmitted signal at the physical layer. In 3G mobile cellular wireless systems, error control coding must accommodate both voice and data users, whose requirements vary considerably in terms of latency, throughput, and the impact of errors on the user application. At the base station, dedicated hardware or readily reconfigurable components are needed to address the concurrent coding and decoding demands of a large number of users with different call parameters. In contrast, the encoder and decoder at the user equipment (UE) are dedicated to a single call setup which changes infrequently. In designing encoder and decoder solutions for 3G wireless systems, not only are the performance issues important, but also the costs. Cellular wireless infrastructure manufacturers need to reduce costs, maximize system reuse, and increase flexibility in order to compete in the market. Furthermore, future-proofing a network is a primary concern due to the high cost of deployment. For the UE, power consumption (battery life) and size are key constraints in addition to manufacturing costs. This article considers the 3G decoder design problem and, using case studies, describes two 3G decoder solutions using ASICs. The first device is targeted for base station deployment and is based on a unified architecture for convolutional and turbo decoding. The second device is a dedicated high-speed radix-4 logMAP turbo decoder targeted for UE, motivated by the requirements for high-speed downlink packet access. Both devices have been fabricated in 0.18 /spl mu/m CMOS technology, and while optimized for either base station or UE, may be used in both applications.

A 28.8 Mb/s 4 /spl times/ 4 MIMO 3G CDMA receiver for frequency selective channels

This paper describes a silicon receiver for a multiple-input multiple-output (MIMO) wireless channel that supports up to 28.8 Mb/s using a 4 /spl times/ 4 QPSK configuration over a 5-MHz frequency selective channel. The architecture has two key components: a space-time equalizer that mitigates both spatial and temporal effects of the channel, and a maximum likelihood detector with approximate a posterior probability (ML-APP) soft estimates of the transmit vectors over the MIMO configuration. The space-time equalizer uses an adaptive tap training process that includes a pilot correlator to reduce adaptation noise. The device is 685 k effective logic gates (11.6 mm/sup 2/) in 0.18-/spl mu/m 6LM CMOS.

A low power normalized-LMS decision feedback equalizer for a wireless packet modem

This paper presents a decision feedback equalizer (DFE) for a high-speed packet modem utilizing the normalized least mean squared (NLMS) tap update algorithm. The equalizer supports up to 43.2 Mbps uncoded data over a wireless channel with a 10% training preamble (48 Mbps with no training). In this work the rapid convergence of the NLMS algorithm is combined a technique for early termination of the tap training process to yield a low power DFE implementation. The low power techniques result in a 43% power reduction over a baseline design. Furthermore, low power synthesis techniques result in an additional 30% power savings on top of the algorithmic power savings.

APP processing for high performance MIMO systems [receiver symbol detector]

One of the most demanding components in a multiple-input multiple-output (MIMO) receiver is the symbol detector. While linear cancellation techniques are typically used, the optimum maximum likelihood (ML) search algorithm combined with soft output processing, e.g. a posteriori probability (APP), offers superior performance and is feasible in current technology. An ASIC can be built for a 4/spl times/4 QPSK detector for HSDPA in less than 1.68 mm/sup 2/ in a 0.18 /spl mu/m process. An MLAPP search grows exponentially as the constellation size is increased, but it is still feasible to achieve near ML performance for 4/spl times/4 16QAM using spherical techniques in a complexity that remains a minor portion of the overall MIMO receiver.