Chris Nicol

A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless

A 24Mb/s 3GPP-HSDPA radix-4 logMAP turbo decoder is designed for 3G data terminals. It features an approximate radix-4 logsum circuit to achieve 145MHz operation. Power is reduced using 1/2-iteration early termination and extrinsics are interleaved in companded format. The decoder core is 14.5mm/sup 2/ in 0.18/spl mu/m CMOS.

A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A 3GPP-compliant 4.1 Mb/s channel decoder supports data and voice calls in a unified Turbo/Viterbi architecture with hardware interleaver memory and pattern computation. The 9 mm/sup 2/ chip in 0.18 /spl mu/m 1.8 V 6LM CMOS operates at 110 MHz and consumes 306 mW when decoding 2 Mb/s data and voice calls.

A low power 128-tap digital adaptive equalizer for broadband modems

This chip provides programmable fractional spacings and slicers making it suitable for 51Mb/s and 155Mb/s ATM over CAT3, as well as for the emerging 100Mb/s base-T2 fast Ethernet standard. The primary design goal is to minimize the power consumption so that the equalizer may be integrated into low-cost single-chip transceivers. Two 64-tap adaptive FIR filters are configured in parallel as in-phase and quadrature filters. Each has a span of l6T, where T is the symbol period, and is programmable to operate with T/2, T/3 or T/4 fractional spacing. On-chip programmable slicers enable slicing of up to 8x8 constellations. They use a reduced constellation for blind training and switch to the full constellation to obtain final convergence. The filters feature a zero latency cascadable systolic FIR structure that has the low power advantages of the direct form due to the reduced number of flip-flops in the output path, as well as the reduced critical path advantages of the transposed form. A programmable delay synchronizes the input data with the coefficients and the error for correct least mean squares (LMS) coefficient adaption with different fractional spacings.

Low power multiplication for FIR filters

This paper describes Booth encoded multipliers and their use in FIR filters and other DSP applications where one input is random and the other is highly correlated. Selecting the correct multiplier configuration for a given application can reduce power by more than 50% depending on the filter response. We show that applying the coefficients of an FIR filter to the Booth encoded input gives less switching activity in the multiplier than when applied to the multiplicand input. We also show that power savings are possible when using time-multiplexed multipliers to compute several filter taps. The techniques are supported with measurements from a full-custom adaptive equalizer chip for broadband communications.

A 28.8 Mb/s 4/spl times/4 MIMO 3G high-speed downlink packet access receiver with normalized least mean square equalization

A receiver for high-speed downlink packet access supporting 28.8 Mb/s using QPSK over a 5 MHz frequency selective 4/spl times/4 MIMO wireless channel (5.76 b/s/Hz). A key feature is the normalized least mean squares space-time equalizer using a pilot correlator for more accurate adaptation. Fabricated in 0.18 /spl mu/m 6M CMOS, the core of the chip covers an 11.6 mm/sup 2/ area.

Integrated circuits for channel coding in 3G cellular mobile wireless systems

Error control coding is a key element of any digital wireless communication system, minimizing the effects of noise and interference on the transmitted signal at the physical layer. In 3G mobile cellular wireless systems, error control coding must accommodate both voice and data users, whose requirements vary considerably in terms of latency, throughput, and the impact of errors on the user application. At the base station, dedicated hardware or readily reconfigurable components are needed to address the concurrent coding and decoding demands of a large number of users with different call parameters. In contrast, the encoder and decoder at the user equipment (UE) are dedicated to a single call setup which changes infrequently. In designing encoder and decoder solutions for 3G wireless systems, not only are the performance issues important, but also the costs. Cellular wireless infrastructure manufacturers need to reduce costs, maximize system reuse, and increase flexibility in order to compete in the market. Furthermore, future-proofing a network is a primary concern due to the high cost of deployment. For the UE, power consumption (battery life) and size are key constraints in addition to manufacturing costs. This article considers the 3G decoder design problem and, using case studies, describes two 3G decoder solutions using ASICs. The first device is targeted for base station deployment and is based on a unified architecture for convolutional and turbo decoding. The second device is a dedicated high-speed radix-4 logMAP turbo decoder targeted for UE, motivated by the requirements for high-speed downlink packet access. Both devices have been fabricated in 0.18 /spl mu/m CMOS technology, and while optimized for either base station or UE, may be used in both applications.

Low power DSP's for wireless communications

Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSPs). In this tutorial, an overview is given of recent developments in DSP processor architectures, that makes them well suited to execute computationally intensive algorithms typically found in communications systems. DSP processors have adapted instruction sets, memory architectures and data paths to execute compute intensive communications algorithms efficiently and in a low power fashion. Basic building blocks include convolutional decoders (mainly the Viterbi algorithm), turbo coding algorithms, FIR filters, speech coders, etc. This is illustrated with examples of different commercial and research processors.

A 28.8 Mb/s 4 /spl times/ 4 MIMO 3G CDMA receiver for frequency selective channels

This paper describes a silicon receiver for a multiple-input multiple-output (MIMO) wireless channel that supports up to 28.8 Mb/s using a 4 /spl times/ 4 QPSK configuration over a 5-MHz frequency selective channel. The architecture has two key components: a space-time equalizer that mitigates both spatial and temporal effects of the channel, and a maximum likelihood detector with approximate a posterior probability (ML-APP) soft estimates of the transmit vectors over the MIMO configuration. The space-time equalizer uses an adaptive tap training process that includes a pilot correlator to reduce adaptation noise. The device is 685 k effective logic gates (11.6 mm/sup 2/) in 0.18-/spl mu/m 6LM CMOS.

A scalable pipelined architecture for fast buffer SRAMs

The design of synchronous buffer SRAMs for packet switching and signal processing applications is described. Called scalable cellular RAM (SCRAM), the approach configures memory blocks in a 2-D array with fully pipelined address and data distribution. The memory is scalable in that the access frequency is determined by the access time of a single block and is independent of the number of blocks. An experimental 0.5 /spl mu/m CMOS 256 Kb SCRAM chip is described that operates at 240 MHz. Simulation results show that larger arrays are feasible using the suggested power reduction and redundancy techniques.

Reconfigurable hardware for efficient implementation of programmable FIR filters

We present the architecture of a programmable FIR filter for use in DSP and communication applications. A filter with this architecture is capable of running a wide variety of single-rate and multirate filtering algorithms with low latency. Flexibility is achieved by distributed register files that store input data and filter coefficients. The functionality of the filter is programmed by a set of pipelined control signals that are independent of the filter length. We demonstrate how to generate these control signals for a variety of configurations. In addition to its flexibility, the architecture is scalable, modular, and has no broadcast signals, making it ideally suited for VLSI implementations.