Mark Andrew Shaw

Silicon Photonics R&D and Manufacturing on 300-mm Wafer Platform

Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated.

Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform

A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.

Qualification of 3D integrated silicon photonics

Recent progress made in Silicon Photonics building blocks has paved the way for large scale industrialisation of devices that can be fabricated in existing CMOS fabs, and recently important steps have also been taken on the industrialisation on 12″ wafers. In this paper we outline the industrialisation of the assembly and test processes required to enable the implementation of Silicon Photonics including the use of 3D face to-face integration of separate electronics and photonics die. We pay particular attention to the qualification procedure of the 3D integrated die, including all the various tests passed during the qualification process. Details are given of the test package used during the 3D qualification used with Thermo-mechanical simulations of the test package.