Mark C. Johnson

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Design and optimization of low voltage high performance dual threshold CMOS circuits

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.

Leakage control with efficient use of transistor stacks in single threshold CMOS

The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

Datapath scheduling with multiple supply voltages and level converters

We present an algorithm called MOVER (Multiple Operating Voltage Energy Reduction) to minimize datapath energy dissipation through use of multiple supply voltages. In a single voltage design, the critical path length, clock period, and number of control steps limit minimization of voltage and power. Multiple supply voltages permit localized voltage reductions to take up remaining schedule slack. MOVER initially finds one minimum voltage for an entire datapath. It then determines a second voltage for operations where there is still schedule slack. New voltages con be introduced and minimized until no schedule slack remains. MOVER was exercised for a variety of DSP datapath examples. Energy savings ranged from 0% to 50% when comparing dual to single voltage results. The benefit of going from two to three voltages never exceeded 15%. Power supply costs are not reflected in these savings, but a simple analysis shows that energy savings can be achieved even with relatively inefficient DC-DC converters. Datapath resource requirements were found to vary greatly with respect to number of supplies. Area penalties ranged from 0% to 170%. Implications of multiple voltage design for IC layout and power supply requirements are discussed.

Software design for low power

It is tempting to suppose that only hardware dissipates power, not software. However, that would be analogous to postulating that only automobiles burn gasoline, not people. In microprocessor, micro-controller, and digital signal processor based systems, it is software that directs much of the activity of the hardware. Consequently, the software can have a substantial impact on the power dissipation of a system. Until recently, there were no efficient and accurate methods to estimate the overall effect of a software design on power dissipation. Without a power estimator there was no way to reliably optimize software to minimize power. Since 1993, a few researchers have begun to crack this problem. In this chapter, you will learn of the progress that has been made and identify ways to minimize the contribution of software to the power dissipation of mixed hardware-software designs.

Optimal selection of supply voltages and level conversions during data path scheduling under resource constraints

In this paper we will consider how to select an optimal set of supply voltages and account for level conversion costs when optimizing the schedule of a resource dominated data path for minimum energy dissipation. An integer linear program (ILP) is presented for minimum energy schedules under latency, supply voltage, and resource constraints. The supply voltage assignment for each resource is modeled as fixed for all time. Schedules were generated for a variety of data path structures, resource and latency constraints. Resource constraints tended to limit the use of reduced supply voltages. With latency constraints loosened to 1.5/spl times/ minimum latency, unlimited resources, and two power supplies, energy savings ranged from 53% to 70% compared to 5 V operation. When resource constraints were applied, savings dropped to a range of 46% to 58%. Loosened latency constraints resulted in increased use of lower supply voltages. With resource constraints un-changed and latency constraints of 2/spl times/ minimum latency, energy savings increased to a range of 64% to 75%. In no case did three supplies decrease energy by more than 5% compared to two supplies.

Multiple-V/sub dd/ scheduling/allocation for partitioned floorplan

We propose a multiple-V/sub dd/ scheduling and allocation scheme for low-power that considers a partitioned floorplan. Multiple-V/sup dd/ designs inevitably introduce an additional power mesh, thus consuming an additional metal layer. Considering voltage partition during scheduling, we may place the resources of same voltage in one partition; thereby reducing the additional power meshes. Such a schedule can also reduce the interfaces between different voltage partitions. Therefore, the logic level-converters and the interconnects can be reduced. To accomplish this, we first generate a multiple-V/sub dd/ schedule using force-directed scheduling. Given resource and time constraints, the multiple-V/sub dd/ scheduler determines the voltage assignment of each node with resource constraints. Next, voltage partitioning is performed. Based on pair-wise and multiple-way graph partitioning, the voltage partitioning algorithm iteratively improves the schedule and the allocation. The proposed scheme generates a multiple-V/sub dd/ schedule for an improved voltage partitioned floorplan. Reduction of level-converter cost, interconnect cost, and the number of voltage clusters were achieved. Relative to the minimum single voltage design, the average energy savings of a multiple-V/sub dd/ partitioned design was 29.7%. Reductions of 33.1%, 28.3%, 51.3% were achieved for level-conversion energy, total bus length and interconnect energy, respectively.

Effects of types of active learning activity on two junior-level computer engineering courses

In several computer engineering and computer science courses, it has been observed that active learning activities (ALAs) aid the students in better understanding of the technical material. In this paper, we explore the influence of the type of the ALA and the academic quality of the student on the effectiveness of the technique. We perform the study in two junior level courses-a course on discrete mathematics as applied to computer engineering topics and an ASIC (Application-Specific Integrated Circuit) design course. The first course has no laboratory component and teaches several abstract mathematical concepts. The latter course deals with the design of digital circuits using the VHDL hardware description language and has a laboratory component. We conduct ALAs of three kinds-solving problems in-class with active participation of the students; homework problems which are worked on collaboratively by the students and with solutions provided later; and, practice examinations handed out before the actual examination which the students are encouraged to solve in groups. The effect on the students is measured through examination questions. Looking at the aggregate class performance, the ALAs through in-class questions and homeworks do not appear to have a significant effect, while the practice examination questions do. However, on segmenting the data, we observe that the ldquoArdquo students benefited from the in-class ALAs while both ldquoArdquo and ldquoBrdquo students benefited from the practice examinations. The worst performing students did not benefit significantly from any of the ALAs. This study leads us to investigate further the possibility of tailoring the ALA to the different learning styles and academic calibers of the students.

Undergraduate dual-core prototyping and analysis of factors influencing student success on dual-core designs

Multi-core techniques are now common even in general computing applications. It is thus critical for our students to be prepared to deal with such systems from both a hardware and software design perspective. In this work, we address the need for multi-core hardware design practice in an undergraduate introductory computer architecture course. Lecture and laboratory materials for a dual-core design sequence were developed in 2007. The new materials have been used each subsequent semester. The yield of functional dual-core designs was 18% for individual students one semester and 56% for student teams of two in another semester. An analysis of student dual-core results indicate that course policies and success on earlier laboratories had a strong impact on the dual-core design yield.