Mark N. Martin

FGMOS dosimetry: design and implementation

We present results from a radiation dosimeter based on the erasure of floating-gate MOS transistors. Background theory and analysis necessary to describe the operation of the sensor are presented.

SPICE macro models for annular MOSFETs

MOSFETs with annular, or enclosed, geometries are now finding frequent use in rad-hard by design (RHBD) approaches to designing custom CMOS ASICs for aerospace applications. Unfortunately, these devices are not accurately modeled by the BSIM3 models normally provided for devices with ordinary rectangular gates. We present a SPICE macro model for an annular n-channel MOSFET to account for the annular geometry effects on gate overlap capacitance and output conductance.

Current-mode differential logic circuits for low power digital systems

A current-mode differential logic scheme is introduced. By biasing in the subthreshold regime, the transistors are operated with maximum normalized transconductance, g/sub m//I. The rapid saturation of devices operated in subthreshold allows for radical scaling of supply voltages to only 300 mV. Application of a back-bias further increases the g/sub m//I of the transistors, and hence the gain of the gates. The back bias also assists in the reduction of stray junction and gate-bulk capacitance. Operating with small voltage swings, delays of a few hundred nanoseconds can be achieved with bias currents of 50 nA. This results in operational speeds of a few megahertz at greatly reduced power consumption compared to standard CMOS digital logic. Experimental results are presented and extrapolated to a scaled version of the circuit.

Power remote input output ASIC (PRIO)

The ability to monitor a variety of voltages and currents is a basic need for spacecraft and other complex systems. Although this function can be performed with a handful of components (FPGA, ADC, op-amps, etc), it is at the expense of board area, mass and power. The power remote I/O (PRIO) ASIC is a single chip, multi-channel monitoring device. The PRIO has internal buffers with externally programmable attenuation to allow the PRIO to safely monitor voltages in the range of -40 V to +40 V DC. The current monitoring is accomplished with an external toroid pickup. The ASIC operates from a 5 V supply and communicates with the spacecraft via the I2C bus

Micro digital solar attitude detector chip

A variety of candidate technologies are usable for an integrated, position-sensitive solar image detector. In most approaches the imaging arrays are read out and analyzed by a microprocessor to determine the apparent position of the sun. In contrast, we have developed a novel active pixel sensor(APS) based design that boasts all the advantages of an active pixel imager and includes analog position computation circuitry on the focal plane. In this work, we describe a Digital Solar Attitude Detector (DSAD) and housekeeping imager ASIC. The ASIC is a 200 pixel by 200 pixel position sensitive APS with associated analog support circuitry. The ASIC is fabricated on a commercial 0.5prn CMOS process. Radiation hardened by design techniques are used to mitigate radiation effects. A single FPGA provides an 12C interface and the total system dissipates less than 20 mW. KeywordsDSAD, Active Pixel Sensors, Imager, Analog Computation

Radiation tolerant mixed signal microcontroller for Martian surface applications

We are developing a radiation tolerant, mixed-signal microcontroller for applications exposed to the Martian surface thermal environment. The part can be used for spacecraft/rover engineering data collection, parameter monitoring, and fault detection at the sensor and needs minimal external support circuits. The 8-bit microcontroller includes timer resources, three serial communications ports, a 16-bit programmable digital interface, an 8-level interrupt controller, and I 2C master/slave bus interface. Mixed signal peripherals include a 16-channel, 10-bit successive approximation A/D converter, 10-bit D/A converter, programmable gain amplifier, and voltage reference. All memory interfaces use a 13-bit wide two-bit error detection, single-bit error correction code for each byte. There is an internal 512 times 13 bit scratchpad static random access memory and 2 Ki times 13 bit electrically erasable programmable read only memory