Mark T. Chan

Architectural enhancements in Stratix V

This paper describes architectural enhancements in the Altera Stratix-V FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric.

Cyclone /spl trade/: a low-cost, high-performance FPGA

This paper describes the Altera Cyclone/spl trade/ FPGA, an architecture specifically designed for low-cost, high-volume applications. An optimized routing architecture, simplified I/O structure, and carefully selected features combine to yield a 57% die size reduction relative to a Stratix/spl trade/ device of similar logic density, with a 7% reduction in performance.

Process variation impact on FPGA configuration memory

The impact of process local variation on FPGA configuration memory is studied in this paper. Memory cell stability is examined by simulations and experiments on 65nm and 45nm processes. A statistical simulation method, which correlates closely with product silicon, has been developed. The results show that the trend of process local variation and memory density scaling adversely impact FPGA configuration memory stability. It is found that the cell stability is greatly affected by cell layout.

A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency multiplication and in-system programmability

A high density programmable logic device (PLD) specifically developed for high performance and for ease of use in production flows is presented. This device is designed on a 0.5 /spl mu/m triple layer metal process to produce a 55 kmil/sup 2/ die size and with the built-in frequency multiplier, allows system performance of up to 140 MHz to be achieved.