Mark W. Morgan

An HDMI Cable Equalizer With Self-Generated Energy Ratio Adaptation Scheme

This brief presents an adaptive equalizer for high-definition-multimedia-interface (HDMI) systems with a new adaptation scheme by comparing the energy ratio in high-frequency and low-frequency bands of the equalized signal with a self-generated energy ratio. The self-generated energy ratio tracks process, voltage, and temperature variations to overcome the problem with preset energy ratio adaptation. Fabricated in 0.5- mum SiGe BiCMOS technology, the adaptive equalizer occupies 0.25 mm2 and consumes 108 mW from 3.3-V voltage supply at 2.25-Gb/s data rate. Measurement results show that it can automatically adapt to up to 10-m HDMI cables, achieving 0.1-UI peak-to-peak jitter in equalized signals.

Low-phase-noise 54GHz quadrature VCO and 76GHz/90GHz VCOs in 65nm CMOS process

This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave Quadrature VCO (QVCO) and VCOs. A transformer coupling with extra phase shift is proposed in QVCO to decouple the tradeoff between phase noise (PN) and phase error and improve the PN performance. This technique is demonstrated in a mmWave QVCO with a measured PN of -119.2 dBc/Hz at 10 MHz offset of a 56.2 GHz carrier and a tuning range of 9.1% (FOMT of -179 dBc/Hz). To our best knowledge, this QVCO has the lowest PN at 10 MHz offset among all the QVCOs around 50-60 GHz frequency range. In addition, an inductive divider feedback technique is proposed in VCO design to improve the transconductance linearity, resulting in larger signal swing and lower PN compared to the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76 GHz VCO and a 90 GHz VCO, both fabricated in a 65 nm CMOS process, with an FOMT of 173.6 dBc/Hz and 173.1 dBc/Hz, respectively.

54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique

This paper presents a novel topology of low-noise amplifier (LNA) with noise reduction and gain improvement. A transformer feedback gm-boosting technique is proposed in a single-ended cascode LNA to reduce the noise figure (NF) and improve the gain simultaneously. Two 54 GHz single-ended cascode LNAs, with transformer and transmission-line for matching, respectively, are demonstrated to verify this technique. Fabricated in a 65 nm CMOS process, the transformer-based (TF-based) LNA exhibits a minimum noise figure (NF) of 3.6 dB at 53.5 GHz and a highest power gain of 28.2 dB at 54 GHz in measurement. To our best knowledge, this LNA has the best noise figure and power gain among all the published V-band CMOS LNAs. The transmission-line-based (TL-based) LNA exhibits a minimum noise figure of 3.8 dB at 53.9 GHz and a highest power gain of 25.4 dB at 54.2 GHz in measurement. Both the LNAs consume 18 mA from a power supply of 1.1 V.

A low-voltage low-power 25 Gb/s clock and data recovery with equalizer in 65 nm CMOS

A novel low-power low-jitter 25 Gb/s clock and data recovery (CDR) circuit with equalizer that can work at an ultra-low supply voltage of 0.6 V is proposed and implemented in a 65 nm CMOS process. A two-tank transformer-feedback technique is proposed in the 25 GHz LC-tank VCO to improve the phase noise performance at low supply voltage. Forward-body biasing (FBB) technique is proposed in the low-voltage signal path to reduce the threshold voltage of the transistors, thus increasing the signal amplitude and achieving low BER. The measurement results show that the CDR and equalizer can work under 0.6 V with 0.23ps/4.62ps (rms/pk-pk) of recovered clock jitter. The measured power consumption of the CDR with the equalizer is 48.8 mW (1.95 mW/Gb/s).

A 5Gb/s automatic sub-bit between-pair skew compensator for parallel data communications in 0.13µm CMOS

A between-pair skew compensator for parallel data communications is presented. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a voltage controlled wide-bandwidth data delay line. A 5Gb/s sub-bit between-pair skew compensator in 0.13µm CMOS occupies 0.03mm2 active die area and dissipates 22.5mW.

A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS

This paper presents a 10Gbps continuous-time FIR receiver equalizer design with a ¼ symbol-period differential self-biased active inductor delay line in 0.12µm CMOS for wired line data communications. The proposed delay line, together with a proposed active inductor Cherry-Hooper transimpedance load at the FIR filter summing node, increases the equalizer speed, while reducing the equalizer power consumption to only 18mW. The prototype occupies 0.03mm2 die area and measurement results show that the equalizer can compensate for 15dB channel loss at 5GHz for 10Gbps data transmission.

A 400MHz-2.4GHz Radiation-Tolerant Self-Biased Phase-Locked Loop

This paper describes the design of a self-biased Phase-Locked Loop for radiation-tolerant applications. A novel single-to-differential converter circuit that eliminates the mismatches on the output of a phase-frequency-detector is proposed to minimize reference spurs. Design considerations for radiation-tolerant design are also described. Fabricated in a 0.25 ¿m CMOS Silicon-on-Sapphire process, the PLL achieves an operating frequency range from 400MHz to 2.4GHz. The RMS jitter of the PLL is 3.9ps at 2.4 GHz.

A 1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4–8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4–100 MHz) with a

A Transformer Feedback

2^{31}-1

{G}_{m}

pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of