Shita Guo

Low-phase-noise 54GHz quadrature VCO and 76GHz/90GHz VCOs in 65nm CMOS process

This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave Quadrature VCO (QVCO) and VCOs. A transformer coupling with extra phase shift is proposed in QVCO to decouple the tradeoff between phase noise (PN) and phase error and improve the PN performance. This technique is demonstrated in a mmWave QVCO with a measured PN of -119.2 dBc/Hz at 10 MHz offset of a 56.2 GHz carrier and a tuning range of 9.1% (FOMT of -179 dBc/Hz). To our best knowledge, this QVCO has the lowest PN at 10 MHz offset among all the QVCOs around 50-60 GHz frequency range. In addition, an inductive divider feedback technique is proposed in VCO design to improve the transconductance linearity, resulting in larger signal swing and lower PN compared to the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76 GHz VCO and a 90 GHz VCO, both fabricated in a 65 nm CMOS process, with an FOMT of 173.6 dBc/Hz and 173.1 dBc/Hz, respectively.

A new compact high-efficiency mmWave power amplifier in 65 nm CMOS process

This paper presents a new design technique for high-efficiency CMOS mmWave power amplifier (PA). The proposed PA adopts NMOS capacitors connected at the gates of the transistors of the last amplifying stage to compensate gate capacitance variation over large signal swing, improving the linearity and the power efficiency. Implemented in 65 nm CMOS process, the presented PA consists of two differential stages, uses baluns, transformers and inductors to realize the input, output, and inter-stage power matching, and achieves a peak PAE of 24.2%, a 6 dB back-off PAE of 10.5% from 3 dB gain compression, a maximum gain of 17 dB, and a 3-dB bandwidth from 68 to 78 GHz.

54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique

This paper presents a novel topology of low-noise amplifier (LNA) with noise reduction and gain improvement. A transformer feedback gm-boosting technique is proposed in a single-ended cascode LNA to reduce the noise figure (NF) and improve the gain simultaneously. Two 54 GHz single-ended cascode LNAs, with transformer and transmission-line for matching, respectively, are demonstrated to verify this technique. Fabricated in a 65 nm CMOS process, the transformer-based (TF-based) LNA exhibits a minimum noise figure (NF) of 3.6 dB at 53.5 GHz and a highest power gain of 28.2 dB at 54 GHz in measurement. To our best knowledge, this LNA has the best noise figure and power gain among all the published V-band CMOS LNAs. The transmission-line-based (TL-based) LNA exhibits a minimum noise figure of 3.8 dB at 53.9 GHz and a highest power gain of 25.4 dB at 54.2 GHz in measurement. Both the LNAs consume 18 mA from a power supply of 1.1 V.

A low-voltage low-power 25 Gb/s clock and data recovery with equalizer in 65 nm CMOS

A novel low-power low-jitter 25 Gb/s clock and data recovery (CDR) circuit with equalizer that can work at an ultra-low supply voltage of 0.6 V is proposed and implemented in a 65 nm CMOS process. A two-tank transformer-feedback technique is proposed in the 25 GHz LC-tank VCO to improve the phase noise performance at low supply voltage. Forward-body biasing (FBB) technique is proposed in the low-voltage signal path to reduce the threshold voltage of the transistors, thus increasing the signal amplitude and achieving low BER. The measurement results show that the CDR and equalizer can work under 0.6 V with 0.23ps/4.62ps (rms/pk-pk) of recovered clock jitter. The measured power consumption of the CDR with the equalizer is 48.8 mW (1.95 mW/Gb/s).

Single-Event Transient Effect on a Self-Biased Ring-Oscillator PLL and an LC PLL Fabricated in SOS Technology

The single-event transient effect on a ring-oscillator based and an LC-tank based phased-locked loop circuits fabricated in a 0.25 μm silicon-on-sapphire technology is analyzed with circuit-level simulations followed by laser experiments. Advantages of the LC-tank based circuits in terms of single-event tolerance over the ring-oscillator based circuits are discussed.

High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process

This brief presents a new design technique for high-efficiency CMOS millimeter-wave power amplifiers (PAs) and the implementations of a two-stage moderate-power PA, a three-stage high-power PA, and a transmitter all working over 68–78 GHz. The proposed PAs adopt nMOS capacitors connected at the gates of the transistors of the last one or two amplifying stages to compensate for the gate capacitance variation over a large signal swing, thus improving the linearity and the power efficiency. Implemented in a 65-nm CMOS process, the two-stage PA achieves a peak power-added efficiency (PAE) of 24.2%, a maximum gain of 17 dB, and a 3-dB bandwidth from 68 to 78 GHz. The three-stage PA achieves a saturated power (Psat) of 17.3 dBm, a peak PAE of 18.9%, and a maximum gain of 21.4 dB. The transmitter consisting of the three-stage PA and a passive double-balanced mixer with local oscillator shaping technique achieves a Psat of 14.6 dBm, a peak efficiency of 13.9%, and a conversion gain of 15.6 dB.

A low-voltage and temperature compensated ring VCO design

A low-voltage, two-stage ring voltage-controlled oscillator (VCO) which can tolerate temperature variation is presented in this paper. Designed using a 0.13 μm CMOS technology, this VCO is capable of operating at 1-V power supply voltage not only for low power consumption, but also to reduce hot-carrier effects and improve reliability and lifetime. It incorporates coarse and fine frequency tuning mainly for tolerance of process variations while achieving small control-voltage-to-frequency gain and enough tuning range of the VCO. Most importantly, a new temperature compensation technique which is suitable for low power supply voltage design is proposed to enable continuous operation of the VCO in variable ambient temperatures environment. Simulations show that with the proposed techniques, the VCO can tolerate process variations, dynamically adapt to different temperatures, and achieve a low temperature sensitivity of 34 ppm/°C over the range from -40°C to 120 °C.

A 1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4–8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4–100 MHz) with a

A Transformer Feedback

2^{31}-1

{G}_{m}

pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of